Abstract: A power supply circuit includes a first power supply, which is electrically coupled to a first power supply terminal and a first ground terminal, and a short-circuit line. The first power supply is adapted to supply the first power supply terminal with a DC voltage having a higher electric potential than the first ground terminal. The short-circuit line is adapted to short-circuit a first data terminal and a second data terminal. The power supply circuit further includes a second power supply electrically coupled to the first ground terminal and the short-circuit line. The second power supply is adapted to supply the first data terminal and the second data terminal with a negative voltage having a lower electric potential than the first ground terminal.

Abstract: A power supply circuit includes a first power supply, which is electrically coupled to a first power supply terminal and a first ground terminal, and a shortcircuit line. The first power supply is adapted to supply the first power supply terminal with a DC voltage having a higher electric potential than the first ground terminal. The shortcircuit line is adapted to short-circuit a first data terminal and a second data terminal. The power supply circuit further includes a second power supply electrically coupled to the first ground terminal and the shortcircuit line. The second power supply is adapted to supply the first data terminal and the second data terminal with a negative voltage having a lower electric potential than the first ground terminal.

Abstract: A data verification method executed by a data verification device that verifies hierarchical structure layout data for a semiconductor device. The method includes retrieving a verification condition that is set in accordance with a data processing system which processes the layout data generated by and provided from a designing device, extracting shaped item existing range information and possessive layout information from the layout data to generate a hierarchical expansion table, cumulating the possessive layout information associated with each cell from an uppermost layer cell of a layout path to a target cell, calculating a cumulative value of the possessive layout information for the layout path, determining whether or not the possessive layout information satisfies the verification condition based on the cumulative value, the verification condition, and the possessive layout information, and determining whether or not the shaped item existing range information satisfies the verification condition.

Abstract: A layout device that reduces work. The layout device includes a storage unit for storing position information of patterns generated through layout designing. A display unit displays the patterns in accordance with a layout corresponding to the position information. An input unit enables a user to designate a pattern from one of the patterns displayed on the display unit as a marked pattern and enables the user to designate a hierarchical level of the hierarchical structure to which the marked pattern belongs as a reference level. A processing unit, connected to the storage unit, the display unit, and the input unit, obtains coordinates of the marked pattern using the position information of the patterns in the reference level that is stored in the storage unit and dumps the obtained coordinates to the display unit.