Abstract: The semiconductor memory device disclosed has a boost circuit, a word drive circuit and a row decoder, and includes a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor, and a second N-channel MOS transistor. The first P-channel MOS transistor and the second P-channel MOS transistor have drains and gates cross-connected and each source and a substrate connected to an output terminal of the boost circuit. The first N-channel MOS transistor has a drain connected to the drain of the first P-channel MOS transistor, a source connected to a ground terminal, and a gate connected to an output terminal of the row decoder. The second N-channel MOS transistor has a source connected to the output terminal of the row decoder, a drain connected to the drain of the second P-channel MOS transistor, and a gate receiving one of a power supply voltage and a control signal.

Abstract: A semiconductor memory device is subjected to a dynamic bias test upon completion of a fabrication process for screening out a product with potential defects, and a block selecting unit incorporated in the semiconductor memory device is responsive to block address bits for allowing an external device to access data bits stored in one of the memory cell blocks, wherein the block selecting unit is further responsive to a test signal indicative of the dynamic bias test for allowing a diagnostic system to write test bits into or read out the test bits from all of the memory cell blocks, thereby quickly completing the dynamic bias test.

Abstract: A semiconductor device fabricated on an n-type substrate has a plurality of signal input terminals each associated with a protection circuit for preventing an internal integrated circuit from being damaged by an undesirable surge voltage. The protection circuit is formed in a p-type well and comprises an n-type impurity region supplied with the surge voltage, an inner well contact area located inside of the n-type impurity region and an outer well contact area located outside of the n-type impurity region, so that a large amount of current flows from both side surfaces of the n-type impurity region into the inner and outer well contact areas, thereby decreasing the voltage level in the p-type well for preventing the p-n junction between the well and the substrate from destruction.