Patents by Inventor Junji Wadatsumi
Junji Wadatsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11334286Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.Type: GrantFiled: November 16, 2020Date of Patent: May 17, 2022Assignee: KIOXIA CORPORATIONInventors: Hiroyuki Kobayashi, Jun Deguchi, Junji Wadatsumi, Takashi Toi
-
Patent number: 11100031Abstract: A memory system includes a first nonvolatile memory, a first bridge circuit connected to the memory, a second nonvolatile memory, a second bridge circuit connected to the second memory and connected to the first circuit, and a controller connected to the first circuit and configured to output, to the first circuit, first data to be stored in the first memory and second data to be stored in the second memory, the first and second data being mapped to multiplexing symbols. The first bridge circuit is configured to, upon receipt of the multiplexing symbols, extract the first data from the symbols, store the first data in the first memory, generate third data based on the second data to insert the generated third data into the multiplexing symbols where the first data was mapped, and output to the second circuit the multiplexing symbols into which the third data has been inserted.Type: GrantFiled: March 2, 2020Date of Patent: August 24, 2021Assignee: KIOXIA CORPORATIONInventors: Koichiro Ban, Tsuyoshi Kogawa, Junji Wadatsumi
-
Publication number: 20210081345Abstract: A memory system includes a first nonvolatile memory, a first bridge circuit connected to the memory, a second nonvolatile memory, a second bridge circuit connected to the second memory and connected to the first circuit, and a controller connected to the first circuit and configured to output, to the first circuit, first data to be stored in the first memory and second data to be stored in the second memory, the first and second data being mapped to multiplexing symbols. The first bridge circuit is configured to, upon receipt of the multiplexing symbols, extract the first data from the symbols, store the first data in the first memory, generate third data based on the second data to insert the generated third data into the multiplexing symbols where the first data was mapped, and output to the second circuit the multiplexing symbols into which the third data has been inserted.Type: ApplicationFiled: March 2, 2020Publication date: March 18, 2021Inventors: Koichiro BAN, Tsuyoshi KOGAWA, Junji WADATSUMI
-
Publication number: 20210064276Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.Type: ApplicationFiled: November 16, 2020Publication date: March 4, 2021Inventors: Hiroyuki KOBAYASHI, Jun DEGUCHI, Junji WADATSUMI, Takashi TOI
-
Patent number: 10838655Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.Type: GrantFiled: February 27, 2018Date of Patent: November 17, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki Kobayashi, Jun Deguchi, Junji Wadatsumi, Takashi Toi
-
Patent number: 10623055Abstract: According to one embodiment, in a reception apparatus, a reception node is capable of being connected to a wired communication channel. A first frequency conversion circuit is electrically connected to the reception node. A second frequency conversion circuit is electrically connected to the reception node. A first adder circuit is electrically connected to the first frequency conversion circuit. A second adder circuit is electrically connected to the second frequency conversion circuit. A first correction circuit is electrically connected between the first frequency conversion circuit and the second adder circuit. A second correction circuit is electrically connected between the second frequency conversion circuit and the first adder circuit. The first correction circuit includes a reverse phase amplifier and a first capacitative element. The second correction circuit includes a positive phase amplifier and a second capacitative element.Type: GrantFiled: March 13, 2018Date of Patent: April 14, 2020Assignee: Toshiba Memory CorporationInventors: Yuta Tsubouchi, Daisuke Miyashita, Junji Wadatsumi, Jun Deguchi
-
Patent number: 10553284Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.Type: GrantFiled: March 13, 2018Date of Patent: February 4, 2020Assignee: Toshiba Memory CorporationInventors: Yuta Tsubouchi, Jun Deguchi, Daisuke Miyashita, Makoto Morimoto, Junji Wadatsumi, Fumihiko Tachibana, Yuji Satoh, Takashi Toi
-
Publication number: 20190087121Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.Type: ApplicationFiled: February 27, 2018Publication date: March 21, 2019Inventors: Hiroyuki KOBAYASHI, Jun DEGUCHI, Junji WADATSUMI, Takashi TOI
-
Publication number: 20190089407Abstract: According to one embodiment, in a reception apparatus, a reception node is capable of being connected to a wired communication channel. A first frequency conversion circuit is electrically connected to the reception node. A second frequency conversion circuit is electrically connected to the reception node. A first adder circuit is electrically connected to the first frequency conversion circuit. A second adder circuit is electrically connected to the second frequency conversion circuit. A first correction circuit is electrically connected between the first frequency conversion circuit and the second adder circuit. A second correction circuit is electrically connected between the second frequency conversion circuit and the first adder circuit. The first correction circuit includes a reverse phase amplifier and a first capacitative element. The second correction circuit includes a positive phase amplifier and a second capacitative element.Type: ApplicationFiled: March 13, 2018Publication date: March 21, 2019Inventors: Yuta Tsubouchi, Daisuke Miyashita, Junji Wadatsumi, Jun Deguchi
-
Patent number: 10236844Abstract: According to an embodiment, an active inductor has a first conductivity type MOS transistor with a source that is connected to an electrical power source supply line and a drain that is connected to an output terminal. It has a capacitance between a gate of the first conductivity type MOS transistor and the electrical power source supply line. It has a diode element that is connected between a drain and a gate of the first conductivity type transistor. It has an electric current source that supplies a bias electric current in a forward direction to the diode element.Type: GrantFiled: September 8, 2017Date of Patent: March 19, 2019Assignee: Toshiba Memory CorporationInventors: Yuta Tsubouchi, Junji Wadatsumi
-
Publication number: 20190074063Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.Type: ApplicationFiled: March 13, 2018Publication date: March 7, 2019Inventors: Yuta Tsubouchi, Jun Deguchi, Daisuke Miyashita, Makoto Morimoto, Junji Wadatsumi, Fumihiko Tachibana, Yuji Satoh, Takashi Toi
-
Publication number: 20180183395Abstract: According to an embodiment, an active inductor has a first conductivity type MOS transistor with a source that is connected to an electrical power source supply line and a drain that is connected to an output terminal. It has a capacitance between a gate of the first conductivity type MOS transistor and the electrical power source supply line. It has a diode element that is connected between a drain and a gate of the first conductivity type transistor. It has an electric current source that supplies a bias electric current in a forward direction to the diode element.Type: ApplicationFiled: September 8, 2017Publication date: June 28, 2018Applicant: Toshiba Memory CorporationInventors: Yuta Tsubouchi, Junji Wadatsumi
-
Patent number: 9203601Abstract: The CDR circuit 100 includes first to second data delaying cells ID1, ID2. The CDR circuit 100 includes first to fourth oscillation delaying cells IC1, IC2, IC3, IC4. The CDR circuit 100 outputs a second data signal d2 at a data output terminal TDout as a recovery data signal Dout. The CDR circuit 100 outputs an oscillation clock signal a0 at a clock output terminal TRCK as a recovery clock signal RCK.Type: GrantFiled: August 21, 2014Date of Patent: December 1, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Junji Wadatsumi, Shouhei Kousai, Daisuke Miyashita
-
Patent number: 9117931Abstract: A semiconductor device according to an embodiment has: a semiconductor substrate; an acoustic resonator formed on the semiconductor substrate, having a semiconductor layer including impurity electrically isolated from the substrate by depletion layer and configured to resonate at a predetermined resonance frequency based on acoustic standing wave excited in the semiconductor layer; a temperature detector formed on the semiconductor substrate and configured to detect temperature of the semiconductor substrate; a calculating unit formed on the semiconductor substrate and configured to perform calculation of temperature compensation based on the temperature detected by the temperature detector, kind of the impurity and concentration of the impurity; and a controller formed on the semiconductor substrate and configured to control the resonance frequency based on a result of the calculation by the calculating unit.Type: GrantFiled: November 27, 2012Date of Patent: August 25, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhide Abe, Atsuko Iida, Kazuhiko Itaya, Junji Wadatsumi, Shouhei Kousai
-
Publication number: 20150103964Abstract: The CDR circuit 100 includes first to second data delaying cells ID1, ID2. The CDR circuit 100 includes first to fourth oscillation delaying cells IC1, IC2, IC3, IC4. The CDR circuit 100 outputs a second data signal d2 at a data output terminal TDout as a recovery data signal Dout. The CDR circuit 100 outputs an oscillation clock signal a0 at a clock output terminal TRCK as a recovery clock signal RCK.Type: ApplicationFiled: August 21, 2014Publication date: April 16, 2015Inventors: Junji Wadatsumi, Shouhei Kousai, Daisuke Miyashita
-
Publication number: 20130256660Abstract: A semiconductor device according to an embodiment has: a semiconductor substrate; an acoustic resonator formed on the semiconductor substrate, having a semiconductor layer including impurity electrically isolated from the substrate by depletion layer and configured to resonate at a predetermined resonance frequency based on acoustic standing wave excited in the semiconductor layer; a temperature detector formed on the semiconductor substrate and configured to detect temperature of the semiconductor substrate; a calculating unit formed on the semiconductor substrate and configured to perform calculation of temperature compensation based on the temperature detected by the temperature detector, kind of the impurity and concentration of the impurity; and a controller formed on the semiconductor substrate and configured to control the resonance frequency based on a result of the calculation by the calculating unit.Type: ApplicationFiled: November 27, 2012Publication date: October 3, 2013Inventors: Kazuhide ABE, Atsuko IIDA, Kazuhiko ITAYA, Junji WADATSUMI, Shouhei KOUSAI
-
Patent number: 8310311Abstract: According to an embodiment, a semiconductor integrated circuit device includes an amplifier and a feedback circuit. The amplifier includes an input terminal receiving an input signal and an output terminal outputting an output signal. The feedback circuit includes a first transistor generating a bias current. The feedback circuit is configured to operate based on the bias current. The feedback circuit is configured to receive the output signal to supply a feedback signal to the input terminal. A signal having a reverse phase to the output signal is input to a gate of the first transistor.Type: GrantFiled: September 21, 2010Date of Patent: November 13, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Junji Wadatsumi
-
Publication number: 20110221532Abstract: According to an embodiment, a semiconductor integrated circuit device includes an amplifier and a feedback circuit. The amplifier includes an input terminal receiving an input signal and an output terminal outputting an output signal. The feedback circuit includes a first transistor generating a bias current. The feedback circuit is configured to operate based on the bias current. The feedback circuit is configured to receive the output signal to supply a feedback signal to the input terminal. A signal having a reverse phase to the output signal is input to a gate of the first transistor.Type: ApplicationFiled: September 21, 2010Publication date: September 15, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Junji Wadatsumi
-
Patent number: 7705663Abstract: A semiconductor integrated circuit, has a current source having one end connected to a power supply and outputting a reference current; a first MOS transistor having one end connected to an other end of the current source and being diode-connected; a second MOS transistor having a gate connected to a gate of the first MOS transistor and passing an output current obtained by current-mirroring the reference current; a first variable resistor connected between an other end of the first MOS transistor and a ground; a resistive component connected between an other end of the second MOS transistor and the ground; and a first operational amplifier fed with a first potential of the other end of the first MOS transistor and a second potential of the other end of the second MOS transistor and outputting a signal for controlling a resistance value of the first variable resistor to equalize the first potential and the second potential, wherein the resistance value of the first variable resistor is controlled based on theType: GrantFiled: March 19, 2008Date of Patent: April 27, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Junji Wadatsumi, Shouhei Kousai
-
Publication number: 20080258779Abstract: A semiconductor integrated circuit, has a current source having one end connected to a power supply and outputting a reference current; a first MOS transistor having one end connected to an other end of the current source and being diode-connected; a second MOS transistor having a gate connected to a gate of the first MOS transistor and passing an output current obtained by current-mirroring the reference current; a first variable resistor connected between an other end of the first MOS transistor and a ground; a resistive component connected between an other end of the second MOS transistor and the ground; and a first operational amplifier fed with a first potential of the other end of the first MOS transistor and a second potential of the other end of the second MOS transistor and outputting a signal for controlling a resistance value of the first variable resistor to equalize the first potential and the second potential, wherein the resistance value of the first variable resistor is controlled based on theType: ApplicationFiled: March 19, 2008Publication date: October 23, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Wadatsumi, Shouhei Kousai