Patents by Inventor Junji Yahiro

Junji Yahiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10665670
    Abstract: A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: May 26, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazutoyo Takano, Kazushige Matsuo, Masayoshi Hirao, Junji Yahiro
  • Publication number: 20190157389
    Abstract: A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.
    Type: Application
    Filed: July 20, 2016
    Publication date: May 23, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazutoyo TAKANO, Kazushige MATSUO, Masayoshi HIRAO, Junji YAHIRO
  • Patent number: 8253163
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: August 28, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Kusunoki, Junji Yahiro, Yoshihiko Hirota
  • Patent number: 8164111
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: April 24, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Kusunoki, Junji Yahiro, Yoshihiko Hirota
  • Publication number: 20110140165
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.
    Type: Application
    Filed: October 7, 2010
    Publication date: June 16, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shigeru KUSUNOKI, Junji Yahiro, Yoshihiko Hirota