Patents by Inventor Junjiang Lei
Junjiang Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10311165Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type features. An initial guiding pattern characterized by a plurality of guiding pattern parameters is constructed for two or more via-type features in a layout design based on target values of location and size parameters for the two or more via-type features. Predicted values of the location and size parameters are then extracted from the initial guiding pattern based on simulations or correlation information between the plurality of guiding pattern parameters and the location and size parameters. Based on the predicted values of the location and size parameters, the target values of location and size parameters and the correlation information, a modified guiding pattern is determined by adjusting one or more parameters of the plurality of guiding pattern parameters. The extraction and determination operations may be iterated.Type: GrantFiled: March 30, 2016Date of Patent: June 4, 2019Assignee: Mentor Graphics CorporationInventors: Junjiang Lei, Le Hong, Yuansheng Ma
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Publication number: 20190146455Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.Type: ApplicationFiled: January 10, 2018Publication date: May 16, 2019Inventors: Daniel Beylkin, Kenneth L. Ho, Sagar Vinodbhai Trivedi, Fangbo Xu, Junjiang Lei, Danping Peng
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Patent number: 9836556Abstract: Aspects of the disclosed technology relate to techniques of optical proximity correction for directed self-assembly guiding patterns. An initial mask pattern for photomask fabrication is first generated by performing a plurality of conventional optical proximity correction iterations. Predicted print errors for two or more via-type features are then determined based on a predicted guiding pattern for the two or more via-type features, a target guiding pattern for the two or more via-type features, and correlation information between a plurality of guiding pattern parameters and location and size parameters for the two or more via-type features. Here the predicted guiding pattern is derived based on the initial mask pattern. Based on the predicted print errors and the correlation information, the initial mask pattern is adjusted to generate a new mask pattern.Type: GrantFiled: March 30, 2016Date of Patent: December 5, 2017Assignee: Mentor Graphics CorporationInventors: Junjiang Lei, Le Hong, Yuansheng Ma
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Publication number: 20160292309Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type features. An initial guiding pattern characterized by a plurality of guiding pattern parameters is constructed for two or more via-type features in a layout design based on target values of location and size parameters for the two or more via-type features. Predicted values of the location and size parameters are then extracted from the initial guiding pattern based on simulations or correlation information between the plurality of guiding pattern parameters and the location and size parameters. Based on the predicted values of the location and size parameters, the target values of location and size parameters and the correlation information, a modified guiding pattern is determined by adjusting one or more parameters of the plurality of guiding pattern parameters. The extraction and determination operations may be iterated.Type: ApplicationFiled: March 30, 2016Publication date: October 6, 2016Inventors: Junjiang Lei, Le Hong, Yuansheng Ma
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Publication number: 20160292348Abstract: Aspects of the disclosed technology relate to techniques of optical proximity correction for directed self-assembly guiding patterns. An initial mask pattern for photomask fabrication is first generated by performing a plurality of conventional optical proximity correction iterations. Predicted print errors for two or more via-type features are then determined based on a predicted guiding pattern for the two or more via-type features, a target guiding pattern for the two or more via-type features, and correlation information between a plurality of guiding pattern parameters and location and size parameters for the two or more via-type features. Here the predicted guiding pattern is derived based on the initial mask pattern. Based on the predicted print errors and the correlation information, the initial mask pattern is adjusted to generate a new mask pattern.Type: ApplicationFiled: March 30, 2016Publication date: October 6, 2016Inventors: Junjiang Lei, Le Hong, Yuansheng Ma
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Patent number: 8910098Abstract: Aspects of the invention relate to techniques for applying edge fragment correlation information to optical proximity correction. Neighbor-aware edge adjustment values for the edge fragments are computed based on edge placement error values and edge fragment correlation information. The computation comprises: selecting a group of edge fragments around a center edge fragment, calculating preliminary neighbor-aware edge adjustment values based on the edge placement error values and the edge fragment correlation information for the group of edge fragments, storing the preliminary neighbor-aware edge fragment adjustment value for the center edge fragment, and repeating the selecting, the calculating and the storing with each of the edge fragments being the center edge fragment. The computed neighbor-aware edge adjustment values are combined with conventional edge adjustment values and the edge fragments are adjusted accordingly. The process may be repeated for a number of times.Type: GrantFiled: February 18, 2014Date of Patent: December 9, 2014Assignee: Mentor Graphics CorporationInventors: Junjiang Lei, Le Hong, Georg P. Lippincott
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Patent number: 8881070Abstract: Aspects of the invention relate to techniques for applying edge fragment correlation information to optical proximity correction. Conventional edge adjustment values for the edge fragments are first derived from edge placement error values. Neighbor-aware edge adjustment values for the edge fragments are then computed based on the edge placement error values, the conventional edge adjustment values and edge fragment correlation information. The computation comprises: calculating pseudo edge placement error values by subtracting neighboring edge movement contribution values from the edge placement error values and calculating the neighbor-aware edge adjustment values based on the pseudo edge placement error values. The computed neighbor-aware edge adjustment values are combined with conventional edge adjustment values and the edge fragments are adjusted accordingly. The process may be repeated for a number of times.Type: GrantFiled: February 18, 2014Date of Patent: November 4, 2014Assignee: Mentor Graphics CorporationInventors: George P. Lippincott, Junjiang Lei, Le Hong
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Patent number: 8677301Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: GrantFiled: June 27, 2012Date of Patent: March 18, 2014Assignee: Cadence Design Systems, Inc.Inventors: Ya-Chieh Lai, Frank Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Patent number: 8645887Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: GrantFiled: June 27, 2012Date of Patent: February 4, 2014Assignee: Cadence Design Systems, Inc.Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Patent number: 8539391Abstract: Aspects of the invention relate to techniques for determining edge fragment correlation information. With various implementations of the invention, image intensity slope information for edge fragments in a layout design is determined. The image intensity slope information comprises information describing how image intensity for each of the edge fragments changes with its position. Image amplitude sensitivity information for the edge fragments is also determined. The image amplitude sensitivity information comprises information describing how image amplitude for each of the edge fragments changes with positions of neighboring edge fragments. Based on the image intensity slope information and the image amplitude sensitivity information, edge fragment correlation information for the edge fragments is determined. Using the edge fragment correlation information, the layout design may be processed by using, for example, OPC techniques.Type: GrantFiled: January 31, 2012Date of Patent: September 17, 2013Assignee: Mentor Graphics CorporationInventors: Junjiang Lei, Le Hong, Mei-Fang Shen, YiNing Pan
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Publication number: 20130198698Abstract: Aspects of the invention relate to techniques for determining edge fragment correlation information. With various implementations of the invention, image intensity slope information for edge fragments in a layout design is determined. The image intensity slope information comprises information describing how image intensity for each of the edge fragments changes with its position. Image amplitude sensitivity information for the edge fragments is also determined. The image amplitude sensitivity information comprises information describing how image amplitude for each of the edge fragments changes with positions of neighboring edge fragments. Based on the image intensity slope information and the image amplitude sensitivity information, edge fragment correlation information for the edge fragments is determined. Using the edge fragment correlation information, the layout design may be processed by using, for example, OPC techniques.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Inventors: Junjiang Lei, Le Hong, Mei Fang Shen, Yi Ning Pan
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Patent number: 8381152Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: GrantFiled: June 5, 2008Date of Patent: February 19, 2013Assignee: Cadence Design Systems, Inc.Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Patent number: 8358828Abstract: A method, system, and computer program product for preprocessing a pattern in a library of patterns and querying a preprocessed library of patterns are disclosed. Embodiments for querying a preprocessed library of patterns are disclosed for determining a distance between the representation for the first pattern and the representation for the second pattern, determining whether the distance between the representation for the first pattern and the representation for the second pattern is within the range for the first pattern, and transforming the second pattern with the transformation matrix to provide information about the second pattern.Type: GrantFiled: December 28, 2007Date of Patent: January 22, 2013Assignee: Cadence Design Systems, Inc.Inventors: Srini Doddi, Junjiang Lei, Kuang-Hao Lay, Weiping Fang
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Patent number: 8341571Abstract: A method, system, and computer program product are disclosed for generating a pattern signature to represent a pattern in an integrated circuit design. In one approach, the method, system and computer program product transform pattern data, two dimensional data for the pattern, into a set of one dimensional mathematical functions, compress the set of one dimensional mathematical functions into a single variable function, compress the single variable function by calculating a set of values for the single variable function, and generate a pattern signature for the pattern from the set of values.Type: GrantFiled: March 7, 2011Date of Patent: December 25, 2012Assignee: Cadence Design Systems, Inc.Inventors: Junjiang Lei, Srini Doddi, Weiping Fang
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Publication number: 20120272200Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Publication number: 20120272201Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Ya-Chieh Lai, Frank Gennari, Matthew Moskewicz, Srinivas Doddi, Junjiang Lei, Weiping Fang, Kuanghao Lay
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Patent number: 8291351Abstract: The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective.Type: GrantFiled: June 1, 2011Date of Patent: October 16, 2012Assignee: Cadence Design Systems, Inc.Inventors: Junjiang Lei, Kuang-Hao Lay, Srini Doddi, Weiping Fang
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Patent number: 8079005Abstract: Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.Type: GrantFiled: September 30, 2008Date of Patent: December 13, 2011Assignee: Cadence Design Systems, Inc.Inventors: Ya-Chieh Lai, Frank E. Gennari, Matthew W Moskewicz, Junjiang Lei, Weinong Lai
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Publication number: 20110239168Abstract: The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective.Type: ApplicationFiled: June 1, 2011Publication date: September 29, 2011Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Junjiang Lei, Kuang-Hao Lay, Srini Doddi, Weiping Fang
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Patent number: 7966586Abstract: The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective.Type: GrantFiled: December 7, 2007Date of Patent: June 21, 2011Assignee: Cadence Design Systems, Inc.Inventors: Junjiang Lei, Kuang-Hao Lay, Srini Doddi, Weiping Fang