Abstract: Aspects of the disclosure relate to use of signal combiners for multiplexing signals. A transmitter may adjust a transmission power of an output signal to compensate for transmission losses associated with the use of signal combiners. The adjustment may be based on a combining mode as indicated by a combiner. The combiner may indicate a combining mode as a voltage level at an output port of the transmitter. If operating in a cascaded mode, the combiner may determine and indicate a cumulative combining mode based on an operating mode/type of the combiner and an operating mode/type as indicated by a downstream combiner.

Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch a single instruction for execution, a decode unit to decode the single instruction into a decoded instruction, wherein the decoded instruction is to cause the graphics processing unit to perform a set of parallel dot product operations on elements of input matrices, and a systolic dot product unit to execute the decoded instruction across one or more parallel processor lanes using multiple systolic layers associated with multiple pipeline stages. The multiple pipeline stages include one or more sets of interconnected multipliers and adders to compute multiple concurrent dot products.

Abstract: A control method for a power source, including the following steps: detecting the electric power quality of multiple channels of inputs of a power source; in response to the electric power quality of the multiple channels of inputs being normal, acquiring and comparing the resistance of a relay when the power source is respectively working at each channel of input; in response to the resistance of the relay at each channel of input meeting a preset condition, acquiring the duration how long each power source is working at one channel of input among the multiple channels of inputs; and in response to the duration how long the power source is working at the channel of input in the multiple channels of inputs being greater than a threshold value, adjusting the power source to work at other channel of input.

Abstract: A control method for a power source, the method including the following steps: detecting the electric power quality of multiple channels of inputs of a power source; in response to the electric power quality of the multiple channels of inputs being normal, acquiring and comparing the resistance of a relay when the power source is respectively working at each channel of input; in response to the resistance of the relay at each channel of input meeting a preset condition, acquiring the duration how long each power source is working at one channel of input among the multiple channels of inputs; and in response to the duration how long the power source is working at the channel of input in the multiple channels of inputs being greater than a threshold value, adjusting the power source to work at other channel of input.

Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes systolic dot product circuitry to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.

Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.

Abstract: The present invention relates to a safety protection device, disclosing an anti-squeezing device for mobile console, comprising: an opening/closing mechanism pivotally mounted in the area of an operating desktop of the mobile console, capable of pivotally opening from a closed state in a direction away from the operator in response to the squeezing thrust of the operator to form a dodging space; and a position signal detection mechanism mounted to detect and transmit an opening/closing position signal of the opening/closing mechanism, so that a control unit of the mobile console may perform control operations based on the opening/closing position signal. The present invention further discloses an application-specific pusher-type anti-squeezing device for mobile console and an aerial work machine.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes systolic dot product circuitry to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

Abstract: A server power supply device and method are provided. The server power supply device includes: a filter capacitor, a voltage collecting unit and a processing unit. One terminal of the filter capacitor is connected to a mains electricity input terminal, the other terminal of the filter capacitor is grounded, and a capacitance of the filter capacitor is greater than a preset standard capacitance. The voltage collecting unit is connected to the mains electricity input terminal and the processing unit, and the voltage collecting unit is configured to collect a first voltage inputted from the mains electricity input terminal. The processing unit is configured to process a current inputted from the mains electricity input terminal based on the first voltage collected by the voltage collecting unit, to generate a first current and supply power to a server with the first current.

Abstract: A power supply system and a power supply method are provided. At least two power supply units are arranged in a power supply cabinet, each of the power supply units includes a main input port and a backup input port. The power supply units are divided into a first power supply group and a second power supply group. The first input power supply is connected to the main input port of each of the power supply units in the first power supply group and the backup input port of each of the power supply units in the second power supply group. The second input power supply is connected to the backup input port of each of the power supply units in the first power supply group and the main input port of each of the power supply units in the second power supply group.

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

Abstract: A server power supply device and method are provided. The server power supply device includes: a filter capacitor, a voltage collecting unit and a processing unit. One terminal of the filter capacitor is connected to a mains electricity input terminal, the other terminal of the filter capacitor is grounded, and a capacitance of the filter capacitor is greater than a preset standard capacitance. The voltage collecting unit is connected to the mains electricity input terminal and the processing unit, and the voltage collecting unit is configured to collect a first voltage inputted from the mains electricity input terminal. The processing unit is configured to process a current inputted from the mains electricity input terminal based on the first voltage collected by the voltage collecting unit, to generate a first current and supply power to a server with the first current.

Abstract: A power supply system and a power supply method are provided. At least two power supply units are arranged in a power supply cabinet, each of the power supply units includes a main input port and a backup input port. The power supply units are divided into a first power supply group and a second power supply group. The first input power supply is connected to the main input port of each of the power supply units in the first power supply group and the backup input port of each of the power supply units in the second power supply group. The second input power supply is connected to the backup input port of each of the power supply units in the first power supply group and the main input port of each of the power supply units in the second power supply group.