Abstract: An apparatus that includes a first stage being coupled to the input terminal to receive an input signal and configured to receive a first bias current. The apparatus further includes a second and a third stage coupled to the first stage being characterized by a first state and a second state. The first state is associated with a first power level and the second state is associated with a second power level lower than the first power level. The third stage comprises a first output and a second output, the first output being configured to provide an output signal coupled to the output terminal and the second output being coupled to the first stage. By utilizing programmable power modes and maintaining a stable bias voltage, the apparatus reduces power consumption and minimizes kickback noise by ensuring smooth switching between power levels.

Abstract: The present disclosure provides a system for mitigating dielectric absorption in a photodiode sensing circuit. The system includes a photodetector array comprising a plurality of photodiode and a sensing circuit coupled to the photodetector array. The sensing circuit comprises a switch matrix configured to selectively route signals from the photodiode, an amplifier array comprising at least one transimpedance amplifier, a reference generator configured to apply a reference voltage to at least one photodiode, and a timing generator configured to control switching between sequence of states of the system, including a sleep state, a pre-charge state, and an active state. The system enables effective mitigation of dielectric absorption by implementing a pre-charge state before transitioning to an active sensing state.

Abstract: A device may include a signal input, an operational amplifier (op-amp) comprising a non-inverting op-amp input coupled to the signal input, an inverting op-amp input, and an op-amp output, a capacitor comprising a plurality of ports and a switched capacitor arrangement. The switched capacitor arrangement includes a first switch coupled between a first capacitor port and the inverting op-amp input, a second switch coupled between a second capacitor port and the op-amp output, a third switch coupled between a third capacitor port and the signal input, and a fourth switch coupled between a fourth capacitor port and ground. The device may process electrophysiology signals by implementing switched-capacitor dual-path DC cancellation to achieve offset and low-frequency interference rejection while maintaining high input impedance and signal amplification.

Abstract: A device is provided herein. The device includes a signal input, an operational amplifier (op-amp) comprising a non-inverting op-amp input, an inverting op-amp input, and an op-amp output, a summer coupled to the op-amp output, a second summer input coupled to the signal input, and a summer output, and a low-pass filter comprising a low-pass filter input coupled to the summer output and a low-pass filter output coupled to the inverting op-amp input. The device processes electrophysiology signals by combining feedforward and feedback paths to achieve DC offset and low-frequency interference rejection while maintaining high input impedance and signal amplification.

Abstract: The subject technology is directed to electronic circuits. In an embodiment, the subject technology provides an apparatus that includes an input terminal configured to receive an input signal. The apparatus further includes a first circuit coupled to the input terminal, the first circuit comprising a first transistor coupled to the input terminal and a level-shifter coupled to the first transistor. A second circuit is coupled to the first circuit, the second circuit comprising a second transistor, the second transistor including a base terminal coupled to a first supply voltage. The apparatus further includes an amplifier comprising a first input and an output, the amplifier being configured to generate an output signal by amplifying the input signal. By optimizing electrostatic discharge (ESD) protection, electrical overstress (EOS) protection, and leakage control in the analog front-end (AFE), the apparatus reduces leakage current and minimizes non-linearity. There are other embodiments as well.

Abstract: An apparatus includes a first circuit that has a photodetector. The photodetector is reverse-biased by a reverse-bias voltage. A common mode voltage is added to the reverse-bias voltage to provide an offset to the photodetector voltage. A second circuit is coupled to the first circuit to provide the common mode voltage for the first circuit. A third circuit is coupled to the second circuit that includes a first voltage source and a second voltage source having opposite voltages equal to half of the reverse-bias voltage. Each one of the first voltage source and the second voltage source are coupled between separate input and output nodes of input and output ports of the third circuit. The first voltage source and the second voltage source provide the reverse-bias voltage to the first circuit to reverse-bias the photodetector. The third circuit provides a photodetector current at an output of the third circuit.

Abstract: A chip short-circuit check method and apparatus, a chip testing method, and a chip and a consumable box are provided. The chip includes a substrate, a grounding terminal, at least two conductive terminals, and a testing portion. The substrate has a first half region and a second half region. The grounding terminal includes a ground wire contact portion configured to be in contact with a stylus of a printer, and located in the first half region. The at least two conductive terminals are located in the second half region and arranged spaced apart from each other. Each conductive terminal includes a contact portion configured to be in contact with the stylus of the printer. The testing portion is located on the substrate and electrically connected to the grounding terminal. The testing portion includes a first testing line segment located between a first conductive terminal and a second conductive terminal.

Abstract: A device includes a first circuit, a ground, a reference voltage source that provides a reference voltage, and a first transistor that includes a first drain, a first source, and a first gate. The first circuit is coupled between the first source and the ground. The device has a second transistor that includes a second source and a second gate. The second transistor is biased as a source follower with the second source of the second transistor being set at the reference voltage. The first gate of the first transistor is coupled to the second gate of the second transistor, the first source has equal voltage as the second source, and the first circuit is coupled between the first source having the reference voltage and the ground to draw a constant current from the first source and to bias the first transistor in the saturation region to reduce parasitic capacitance.

Abstract: An apparatus includes a digital ramp generator comprising a delay line, the delay line comprising one or more delay elements and an oscillator, wherein the digital ramp generator is configured to generate a code based on respective outputs of the one or more delay elements, a digital to analog converter coupled to the digital ramp generator, wherein the digital to analog converter is configured to generate a reference signal, wherein the reference signal is generated based, at least in part, on the code, and a driver coupled to the digital to analog converter, the driver configured to generate a drive current based, at least in part, on the reference signal.

Abstract: An apparatus includes a first circuit that has a photodetector. The photodetector is reverse-biased by a reverse-bias voltage. A common mode voltage is added to the reverse-bias voltage to provide an offset to the photodetector voltage. A second circuit is coupled to the first circuit to provide the common mode voltage for the first circuit. A third circuit is coupled to the second circuit that includes a first voltage source and a second voltage source having opposite voltages equal to half of the reverse-bias voltage. Each one of the first voltage source and the second voltage source are coupled between separate input and output nodes of input and output ports of the third circuit. The first voltage source and the second voltage source provide the reverse-bias voltage to the first circuit to reverse-bias the photodetector. The third circuit provides a photodetector current at an output of the third circuit.

Abstract: An apparatus for detecting optical signals includes a photodetector. The photodetector is reverse-biased by a first voltage and a second voltage is added to the first voltage to provide an offset equal to the second voltage for the photodetector. A first circuit is coupled to the first circuit to provide the second voltage for the photodetector and a second circuit is coupled to the first circuit to provide the first voltage to the photodetector to reverse-bias the photodetector. The second circuit provides an output voltage proportional to a current of the photodetector at an output of the second circuit.

Abstract: An apparatus for detecting optical signals includes a photodetector. The photodetector is reverse-biased by a first voltage and a second voltage is added to the first voltage to provide an offset equal to the second voltage for the photodetector. A first circuit is coupled to the first circuit to provide the second voltage for the photodetector and a second circuit is coupled to the first circuit to provide the first voltage to the photodetector to reverse-bias the photodetector. The second circuit provides an output voltage proportional to a current of the photodetector at an output of the second circuit.

Abstract: A device includes a first circuit, a ground, a reference voltage source that provides a reference voltage, and a first transistor that includes a first drain, a first source, and a first gate. The first circuit is coupled between the first source and the ground. The device has a second transistor that includes a second source and a second gate. The second transistor is biased as a source follower with the second source of the second transistor being set at the reference voltage. The first gate of the first transistor is coupled to the second gate of the second transistor, the first source has equal voltage as the second source, and the first circuit is coupled between the first source having the reference voltage and the ground to draw a constant current from the first source and to bias the first transistor in the saturation region to reduce parasitic capacitance.

Abstract: An apparatus includes a digital ramp generator comprising a delay line, the delay line comprising one or more delay elements and an oscillator, wherein the digital ramp generator is configured to generate a code based on respective outputs of the one or more delay elements, a digital to analog converter coupled to the digital ramp generator, wherein the digital to analog converter is configured to generate a reference signal, wherein the reference signal is generated based, at least in part, on the code, and a driver coupled to the digital to analog converter, the driver configured to generate a drive current based, at least in part, on the reference signal.

Abstract: An envelope tracking device includes circuitry that senses a current of an input state of the envelope tracking device. The circuitry also senses an output voltage of the envelope tracking device, and turns on at least one of a first and a second output switches to generate an output current based on at least one of the sensed current and the sensed voltage.

Abstract: A device, a circuit, and a method for current bypass are provided. The device includes circuitry detects an overload condition at a switching regulator output, enables a current bypass path including a linear current source in response to detecting the overload condition, and digitizes a difference between a load current and a switching regulator output current. The linear current source generates an active current assist signal based on the digitized difference between the load current and the switching regulator output current.

Abstract: An envelope tracking device includes circuitry that senses a current of an input state of the envelope tracking device. The circuitry also senses an output voltage of the envelope tracking device, and turns on at least one of a first and a second output switches to generate an output current based on at least one of the sensed current and the sensed voltage.

Abstract: A device, a circuit, and a method for current bypass are provided. The device includes circuitry detects an overload condition at a switching regulator output, enables a current bypass path including a linear current source in response to detecting the overload condition, and digitizes a difference between a load current and a switching regulator output current. The linear current source generates an active current assist signal based on the digitized difference between the load current and the switching regulator output current.

Abstract: Described are methods and apparatuses, including computer program products, for automatically updating a tag embedded in a webpage that summarizes a current version of the webpage. A first model representative of the current version of the webpage is extracted. The first model is compared with a second model corresponding to a previous version of the webpage to detect one or more changes to the webpage. If the changes exceed a threshold, at least one keyword is determined for to the current version of the webpage. The tag of the webpage can be updated to include the keyword.