Patents by Inventor Junjie PENG

Junjie PENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11643758
    Abstract: The application relates to the technical field of wiring accessories, in particular to a protective tube. The protective tube includes a tube wall and fluffy warp yarns, wherein the tube wall forms a pipeline for a cable to be threaded therein and includes cross-woven first warp yarns and first weft yarns; the fluffy warp yarns are on an inner surface of the tube wall and are fluffier than the first warp yarns, the fluffy warp yarns are cross-woven with the first weft yarns and form a plurality of intersections with the first weft yarns, and each of the fluffy warp yarns spans a plurality of the first weft yarns between two adjacent intersections. When the protective tube is subjected to external impact, the tube wall with stronger hardness can protect the cable; moreover, the fluffy warp yarn reduce the friction between the protective tube and the cable.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 9, 2023
    Assignee: SHENZHEN JDD TECH NEW MATERIAL CO., LTD.
    Inventors: Yaojun Gao, Baohui Zhang, Fengkai Yang, Qiaoyun Yang, Junjie Peng, Wei Zhou, Bosen Long
  • Patent number: 11444607
    Abstract: Disclosed is a many-bit, groupable, reconfigurable, multi-valued, electronic operator and its construction method. Each bit of the electronic operator is provided with n column calculators and one potential combiner. A data input line is connected to an input terminal of an A signal selector, and an output terminal of the A signal selector is connected to a work permitter. Another input terminal of the work permitter is connected to a reconfiguration latch, and an output terminal of the work permitter is further connected to an output validator. Another input terminal of the output validator is connected to a power supply Vcc, and an output terminal of the output validator is connected to an output generator. Another input terminal of the output generator is connected to a reconfiguration circuit, and an output terminal of the output generator is connected to the potential combiner.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 13, 2022
    Inventors: Yi Jin, Shan Ouyang, Ying Wang, Yunfu Shen, Junjie Peng, Shiqiang Zhou, Yuejun Liu, Xunlei Chen
  • Publication number: 20210310160
    Abstract: The application relates to the technical field of wiring accessories, in particular to a protective tube. The protective tube includes a tube wall and fluffy warp yarns, wherein the tube wall forms a pipeline for a cable to be threaded therein and includes cross-woven first warp yarns and first weft yarns; the fluffy warp yarns are on an inner surface of the tube wall and are fluffier than the first warp yarns, the fluffy warp yarns are cross-woven with the first weft yarns and form a plurality of intersections with the first weft yarns, and each of the fluffy warp yarns spans a plurality of the first weft yarns between two adjacent intersections. When the protective tube is subjected to external impact, the tube wall with stronger hardness can protect the cable; moreover, the fluffy warp yarn reduce the friction between the protective tube and the cable.
    Type: Application
    Filed: March 13, 2020
    Publication date: October 7, 2021
    Inventors: Yaojun Gao, Baohui Zhang, Fengkai Yang, Qiaoyun Yang, Junjie Peng, Wei Zhou, Bosen Long
  • Publication number: 20210132906
    Abstract: Disclosed is a method for configuring an MSD parallel adder based on ternary logic operators. Five ternary logic operators that satisfy a sufficient condition for MSD addition are used to configure an MSD parallel adder. During the arrangement of a ternary logic operator, any method in the following may be used: each of ternary operators of n bits is reconfigured into a ternary logic operator each time, and reconfiguration is performed five times for implementation; each of ternary operators of n bits is reconfigured into two ternary logic operators having the same input each time, and reconfiguration is performed three times for implementation; each of ternary operators of n bits is reconfigured into five ternary logic operators of the same time, and reconfiguration is performed once for implementation; corresponding unreconfigurable ternary logic operators are used instead for the foregoing reconfiguration process.
    Type: Application
    Filed: December 11, 2020
    Publication date: May 6, 2021
    Inventors: Yi JIN, Yunfu SHEN, Shan OUYANG, Junjie PENG, Junjie ZHANG, Hongjian WANG
  • Publication number: 20210119615
    Abstract: Disclosed is a many-bit, groupable, reconfigurable, multi-valued, electronic operator and its construction method. Each bit of the electronic operator is provided with n column calculators and one potential combiner. A data input line is connected to an input terminal of an A signal selector, and an output terminal of the A signal selector is connected to a work permitter. Another input terminal of the work permitter is connected to a reconfiguration latch, and an output terminal of the work permitter is further connected to an output validator. Another input terminal of the output validator is connected to a power supply Vcc, and an output terminal of the output validator is connected to an output generator. Another input terminal of the output generator is connected to a reconfiguration circuit, and an output terminal of the output generator is connected to the potential combiner.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Yi JIN, Shan OUYANG, Ying WANG, Yunfu SHEN, Junjie PENG, Shiqiang ZHOU, Yuejun LIU, Xunlei CHEN
  • Patent number: 10042759
    Abstract: A computer system includes an addressing assembly, connected respectively to high bits of a memory address line of a processor and high bits of a word address line of a storage, and used to convert, in a preset continuous or discrete range on the storage, high bits of a memory address formed by the processor into high bits of a corresponding word address of the storage and output the high bits to the storage. Low bits of the memory address line of the processor are connected to low bits of the word address line of the storage. The preset range is smaller than or equal to an addressing range of the memory address line of the processor. The processor changes storage units of the storage covered by the preset range by changing the preset range. Thus it reduces cost, improves operation efficiency, shortens operation time, and has wide applicability.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 7, 2018
    Assignee: SHANGHAI UNIVERSITY
    Inventors: Yi Jin, Shan Ouyang, Yunfu Shen, Junjie Peng, Xuemin Liu
  • Publication number: 20170153974
    Abstract: A computer system includes an addressing assembly, connected respectively to high bits of a memory address line of a processor and high bits of a word address line of a storage, and used to convert, in a preset continuous or discrete range on the storage, high bits of a memory address formed by the processor into high bits of a corresponding word address of the storage and output the high bits to the storage. Low bits of the memory address line of the processor are connected to low bits of the word address line of the storage. The preset range is smaller than or equal to an addressing range of the memory address line of the processor. The processor changes storage units of the storage covered by the preset range by changing the preset range. Thus it reduces cost, improves operation efficiency, shortens operation time, and has wide applicability.
    Type: Application
    Filed: June 19, 2014
    Publication date: June 1, 2017
    Inventors: YI JIN, Shan OUYANG, Yunfu SHEN, Junjie PENG, Xuemin LIU
  • Patent number: D870062
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 17, 2019
    Inventor: Junjie Peng