Abstract: Aspects disclosed herein include a die interconnect structure with embedded inductor(s) including coupled coils formed in redistribution layer (RDL) and adjacent bump-level distribution layer (BDL) for improved Q factor. The die interconnect structure includes a metal pad and a first coil formed in the RDL. The die interconnect structure also includes the BDL which includes a secondary metal pad and a second coil. The die interconnect structure also includes a seed layer between the first coil and the second coil. The die interconnect structure includes an inductor comprising the first coil, the second coil, and a via coupling the first and second coils. In this manner, the additional second coil formed in the BDL has higher conductance, less resistance than a coil formed in metallization layers within the die and, thus, advantageously improving the Q factor of the inductor.

Abstract: A self-aligned contact (SAC) and method for making the same is disclosed. In an aspect a field effect transistor (FET) structure comprises a channel connecting a first source or drain (S/D) region to a second S/D region, a gate structure, comprising a multi-layer metal gate between gate spacers, disposed above a gate region that at least partially surrounds the channel, a self-alignment structure, also referred to as a “hat”, disposed above the gate structure and covering at least the multi-layer metal gate and the gate spacers, and a first S/D contact that is self-aligned to the hat and connected to the first S/D region. During fabrication, a self-assembly monolayer (SAM) is used to precisely align the hat over the multi-layer metal gate. The S/D contacts are then self-aligned to the hat, even if the etch mask has an overlay error. The hat also shields the gate structure during an etch.

Abstract: Deep vias may be employed on a die to connect transistor circuits on a front side to a power distribution network on a back side. Deep vias extending from a second die surface to a first die surface over an entire length may have high resistance interfaces to circuit interconnects that couple the deep vias to transistor circuits. Deep vias adjacent to transistor channel regions in the transistor circuits may also cause unwanted capacitance. An exemplary deep via includes an interface region and at least one non-interface region, where the interface region includes an interface between the deep via and a circuit interconnect, and the at least one non-interface region extends a second distance that is less than the distance between the first die surface and the second die surface. In this manner, capacitance is reduced, and resistance may be reduced.

Abstract: An integrated circuit (IC) is described. The IC includes a substrate as well as an interlayer dielectric (ILD) layer adjacent to the substrate. The IC also includes a front-end-of-line (FEOL) layer between the substrate and the ILD layer. The IC further includes back-end-of-line (BEOL) metal interconnects in the ILD layer. The IC also includes a through silicon via (TSV), partially extending through the ILD layer, landing on a first metal layer interconnect of the BEOL metal interconnects. A critical dimension (CD) of the TSV is greater than or equal to a width of the first metal layer interconnect.

Abstract: A logic circuit includes a first circuit having a first diffusion region and a second diffusion region and a second circuit having a third diffusion region, and a fourth diffusion region. First devices in the first circuit each include a portion of the first diffusion region and a portion of the second diffusion region. Second devices in the second circuit each include portions of the third and fourth diffusion regions. The first diffusion region is between the second diffusion region and the third diffusion region. The third diffusion region is between the first diffusion region and the fourth diffusion region. A second distance from a first side of the fourth diffusion region to a second side of the third diffusion region is less than a first distance from a first side of the first diffusion region to a second side of the second diffusion region.

Abstract: A three-dimensional (3D) memory structure is described. The 3D memory structure includes a first memory die having first multilayer contact pads including a first outer pad composed of a first conductive material. The 3D memory structure also includes a base logic die including second multilayer contact pads having a second outer pad composed of the first conductive material. The 3D memory structure further includes hybrid bonding links coupled between the second outer pad of the second multilayer contact pads of the base logic die and the first outer pad of the first multilayer contact pads of the first memory die. The hybrid bonding links are composed of the first conductive material.

Abstract: A three-dimensional (3D) stacked chip is described. The 3D stacked chip includes a carrier substrate. The 3D stacked chip also includes a die having a back-end-of-line (BEOL) layer bonded to the carrier substrate through a bonding layer and an active layer coupled between the BEOL layer and a redistribution layer (RDL). The 3D stacked chip further includes dummy stacked vias extending through the BEOL layer, between the active layer and the carrier substrate.

Abstract: Disclosed are devices that include a direct N/P local interconnect with minimal recess on shallow trench isolation (STI) oxide. This reduces undesirable coupling capacitance with active gate, which in turn improves AC performance of the device. Pull or even partial replacement of STI oxide with low-k dielectric can further reduce coupling capacitance.

Abstract: Aspects disclosed include a semiconductor die including a conductive bridge comprising a metal via coupling two adjacent metal interconnects in a single metal layer to address tiger tooth defects. The die includes a first dielectric layer in which the two adjacent metal interconnects are formed. The metal via is coupled to the top surface of the two adjacent metal interconnects and extends over the top surface of the first dielectric layer between the two adjacent metal interconnects. The conductive bridge includes a portion of the two adjacent metal interconnects coupled to the bottom surface of the metal via and a dielectric protection layer between the bottom surface of the metal via and the top surface of the first dielectric layer and co-extensive with the bottom surface of the metal via. The two adjacent metal interconnects do not have any intervening metal interconnects between them.

Abstract: A chip includes a combined capacitor. The combined capacitor includes a frontside capacitor, a backside capacitor, and vertical coupling structures coupling the frontside capacitor and the backside capacitor in parallel.

Abstract: A fin field effect transistor (FinFET) is described. The FinFET includes a substrate and a shallow trench isolation (STI) region on the substrate. The FinFET also includes a first fin structure on the substrate and extending through the STI region. The FinFET further includes a second fin structure on the substrate and extending through the STI region. The FinFET also includes a metal gate on the STI region, on the first fin structure, and on the second fin structure. The metal gate is composed of a first sub-metal gate cut line filled with a first stressor material, and a second sub-metal gate cut line filled with a second stressor material different from the first stressor material.

Abstract: A chip includes a first source/drain, a second source/drain, and a gate between the first source/drain and the second source/drain, wherein the gate includes a ledge extending from a first side of the gate. The chip also includes one or more channels coupled between the first source/drain and the second source/drain, wherein the one or more channels pass through the gate. The chip further comprises a gate coupling structure disposed on the gate.

Abstract: A chip includes an active device, a first backside thermally conductive layer, and a second backside thermally conductive layer, wherein the first backside thermally conductive layer is between the active device and the second backside thermally conductive layer. The chip also includes a first via electrically coupled to the active device, wherein the first via extends through the first backside thermally conductive layer, and a first metal path electrically coupled to the first via, wherein the first metal path extends through the second backside thermally conductive layer.

Abstract: A chip includes an active device, a first backside silicon layer disposed below the active device, a first backside metal path electrically coupled to the active device and extending through the first backside silicon layer, and a first electrical barrier disposed between one or more sides of the first backside metal path and the first backside silicon layer.

Abstract: An integrated circuit (IC) is described. The IC includes a dielectric layer of a first dielectric material. The IC also includes a first metal layer in the dielectric layer. The first metal layer has a first adhesion layer on a backside surface, a second adhesion layer on a frontside surface of the first metal layer. Additionally, the first metal layer has dielectric alignment structures on the second adhesion layer of a second dielectric material different from the first dielectric material. The IC further includes a second metal layer landing on the second adhesion layer on the frontside surface of the first metal layer, between the dielectric alignment structures.

Abstract: Aspects disclosed include a semiconductor die including a transistor coupled to a contact layer wherein the contact layer includes a metal contact having a sidewall with a reduced height to promote connectivity with an adjacent via. The die comprises the contact layer adjacent to an epitaxial layer of the transistor. The contact layer comprises a metal contact adjacent to the epitaxial layer and having a first height. The metal contact comprises a plurality of sidewalls wherein at least one of the plurality of sidewalls has a second height which is less than the first height resulting in increased metal at a surface of the metal contact. The die further comprising a via layer adjacent to the contact layer. The via layer comprising a via adjacent to the surface of the metal contact increasing the connectivity between the via and the metal contact.

Abstract: A semiconductor structure having a high-temperature silicide contact for backside source/drain (S/D) contacts and method for making the same is disclosed. In an aspect, the semiconductor structure comprises a substrate; a source/drain (S/D) structure comprising a lower S/D portion disposed above the substrate and an upper S/D portion disposed above the lower S/D portion, the lower S/D portion comprising a high temperature silicide structure and an etch stop material structure surrounding at least a portion of the high temperature silicide structure, the upper S/D portion comprising an epitaxial (EPI) material in contact with the high temperature silicide structure; and a backside metal structure that extends through the substrate and is in contact with the high temperature silicide structure.

Abstract: An IC includes a first source/drain region of a first transistor in a semiconductor substrate coupled to a first, frontside metallization layer through a metal contact and a low resistance layer (e.g., silicide layer) formed at a high temperature. A second source/drain region of a second transistor is coupled to a second, backside metallization layer(s) though a backside metal contact and a germanide layer. The germanide layer may be formed between the metal contact and a semiconductor material of the source/drain region at a lower temperature (e.g., 350° C.) than is used in the process to form low resistance (e.g., silicide) layers (e.g., 700° C.). Germanide layers reduce resistance of electrical paths between source/drain regions of transistors and backside metal contacts compared to silicide layers formed at the same lower temperatures and avoid the high temperatures that may cause damage to metallization layers on the integrated circuit (IC).

Abstract: A semiconductor structure having metallization airgaps for subtractive metal processes and a method for making the same are disclosed. In an aspect, the semiconductor structure includes metal traces disposed above an adhesion layer and separated from each other in a horizontal direction by one or more airgaps having a height H. A dielectric layer is disposed above the metal traces but not above the airgaps. An etch stop layer (ESL) is disposed above the first dielectric layer and the airgaps. Each airgap extends from the top surface of the adhesion layer to the bottom surface of the first ESL and has a width that extends in the second horizontal direction from a side surface of the first metal trace, from a side surface of the second metal trace, or from the first metal trace to the second metal trace, depending on the pitch of the metal traces.

Abstract: Aspects disclosed include a semiconductor die including a transistor coupled to a contact layer wherein the contact layer includes a metal contact having a sidewall with a reduced height to promote connectivity with an adjacent via. The die comprises the contact layer adjacent to an epitaxial layer of the transistor. The contact layer comprises a metal contact adjacent to the epitaxial layer and having a first height. The metal contact comprises a plurality of sidewalls wherein at least one of the plurality of sidewalls has a second height which is less than the first height resulting in increased metal at a surface of the metal contact. The die further comprising a via layer adjacent to the contact layer. The via layer comprising a via adjacent to the surface of the metal contact increasing the connectivity between the via and the metal contact.