Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

Abstract: A display control apparatus includes a comparison control unit which performs a cyclic redundancy check over an arbitrary region of image data. The comparison control unit includes a region control unit which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit which performs arithmetic processing for the cyclic redundancy check over a region selected by the region control unit, and a comparison circuit which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value. Error detection by the cyclic redundancy check is performed only on the target region of the cyclic redundancy check in the arbitrary region, which facilitates the cyclic redundancy check.

Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

Abstract: To enable an instrument panel to appropriately check whether or not data display is normal. A display control apparatus includes a display output control unit and a CPU. The display output control unit includes a comparison control unit which performs a cyclic redundancy check over an arbitrary region of image data. The comparison control unit includes a region control unit which selects a region of the image data based on comparison region information for specifying an arbitrary region of the image displayed on the display unit as a cyclic redundancy check target region, an arithmetic processing unit which performs arithmetic processing for the cyclic redundancy check over a region selected by the region control unit, and a comparison circuit which performs error detection by comparing the result of the arithmetic processing by the arithmetic processing unit with its expected value.

Abstract: A bus control system that reduces power consumption with a relatively simple structure. Load input signals are respectively provided to input capture registers. A free running counter provides each input capture register with a counter signal through a timer bus. A latch circuit is arranged in the timer bus. Capture conditions of each load input signal is input to an OR circuit connected to the latch circuit. When the capture conditions of at least one load input signal are satisfied, the latch circuit provides each input capture register with a counter signal.

Abstract: The objective is to provide an electronic control apparatus capable of overwriting data in a nonvolatile memory, even during control operation. An ECU (10) includes a CPU (100), a flash EEPROM 101, and a calibration RAM (102). When calibration is performed, data in a calibration area of the flash EEPROM (101) is stored into the calibration RAM (102). A memory area of the calibration RAM (102) is overlapped over the calibration area to perform calibration. The data in the calibration area is written into the calibration RAM (102). When the calibration is completed, a super-user mode is entered in which the data stored in the calibration RAM (102) is written into the flash EEPROM (101) by use of a control register (113).

Abstract: As the signal lines, such as the data bus, become longer, signal delay occurs due to the resistance and capacitance components of that bus. In order to minimize the effect due to this delay, the processing module is designed in consideration of the delay time. An interface circuit 13 is provided in the bus to control the signal transfer. Data and so forth sent from the central processing unit is supplied directly to the extended bus without being delayed in the interface circuit. Data signals and so forth transferred to the central processing unit 11 is delayed for a predetermined time in the latch 25 of the interface circuit before being sent to the central processing unit. Because only the data signal to be sent to the central processing unit is latched, the size of the interface circuit can be minimized.