Abstract: In a case where a determination section (34) determines that a distance between rp and wp is less than RDIST, a period control section (33) carries out a suspending control of a reading operation of a next line, until the distance between rp and wp is not less than RDIST.

Abstract: The present invention includes a write-in start position control section (36) that performs a process of shifting, by a given shifting amount, a start position of a write-in operation to the frame memory (31), when the write-in operation is started, the given shifting amount being predetermined so as not to exceed a capacity reserved in advance in the frame memory.

Abstract: To prevent tearing in a case where image data is compressed to be written into a frame memory, the present invention includes (i) a compression section (33) for compressing image data for a single frame, the image data being transferred from a host processor (2), and writing the image data into a frame memory (31), (ii) an expansion section for reading image data, expanding the image data, and transferring the image data to an LCD (4), and (iii) a delay control section (32) for, until an inhibit time period Ts passes after the start of reading image data for a first frame, inhibiting the start of writing image data.

Abstract: An object of the present invention is to provide a display device which suppresses power consumption as well as displaying an image with excellent quality. A display device (1) in accordance with one aspect of the present invention includes a polarity determining section (35) for determining whether or not a first polarity in a drive vertical period immediately preceding a first term in which an image is not rewritten is the same as a second polarity in a pause vertical period which is a last pause vertical period before the second vertical period, and a refresh control section (34) for providing an additional vertical period in the first term in a case where the first polarity is the same as the second polarity.

Abstract: The display controller (1) includes: a DRAM (31); a SRAM (32) which consumes electric power less than the DRAM (31); an update judging section (61); a secondary compression section (70); and a decompression section (40). In a case where the update judging section (61) has judged that image data is not updated, (i) the secondary compression section (70) compresses image data and then stores compressed image data in the SRAM (32), (ii) the DRAM (31) stops a memory retaining operation, and (iii) the decompression section (40) decompresses the compressed image data and then supplies decompressed data to an LCD (3).

Abstract: To prevent tearing in a case where image data is compressed to be written into a frame memory, the present invention includes (i) a compression section (33) for compressing image data for a single frame, the image data being transferred from a host processor (2), and writing the image data into a frame memory (31), (ii) an expansion section for reading image data, expanding the image data, and transferring the image data to an LCD (4), and (iii) a delay control section (32) for, until an inhibit time period Ts passes after the start of reading image data for a first frame, inhibiting the start of writing image data.

Abstract: A memory control device of the present invention comprises a determination section (34) for determining whether a time point of start of a writing operation falls within a risky period; and a delay control section (32) for delaying, in a case where the determination section (34) determines that the time point of the start of the writing operation falls within the risky period, a time point of the start of one of the writing operation and the reading operation which one is higher in operation rate, said one of the writing operation and the reading operation being delayed by a predetermined delay period.

Abstract: In a case where next image data, corresponding to a next screen, is not supplied from a host even when first predetermined time has elapsed since the first supply of image data was completed, the period control section (32) starts the second supply of the image data, of which the first supply has been carried out, to a liquid crystal display device. In a case where next image data, corresponding to a next frame, is not supplied from the host even when second predetermined time has elapsed since the second supply of the image data was completed, the period control section (32) starts the third supply of the image data to the liquid crystal display device, and sets the first predetermined time to be longer than the second predetermined time. This makes it possible to appropriately update a displayed image.

Abstract: A memory control device of the present invention comprises a reset control section (32) for (i) suspending, at a time point where rp overtakes wp or wp overtakes rp or a time point immediately before that time point, a reading operation of data, and (ii) conducting again, at a predetermined time point where reading is to be resumed, the reading operation of the data from a position at which the reading operation has been started in a frame memory (31).

Abstract: The present invention includes a write-in start position control section (36) that performs a process of shifting, by a given shifting amount, a start position of a write-in operation to the frame memory (31), when the write-in operation is started, the given shifting amount being predetermined so as not to exceed a capacity reserved in advance in the frame memory.

Abstract: In a case where a determination section (34) determines that a distance between rp and wp is less than RDIST, a period control section (33) carries out a suspending control of a reading operation of a next line, until the distance between rp and wp is not less than RDIST.

Abstract: In a conventional gated clock generating circuit, different signal delay times are produced depending on the arrangement of interconnection of circuit elements, often causing glitches. To avoid this, a gated clock generating circuit of the invention has a circuit that generates a first gate signal having inversion points synchronous with edges of a continuously pulsating clock signal, a circuit that generates a second gate signal deviated by half the period of the clock signal relative to the first gate signal, and a circuit that turns on and off the output of the clock signal in accordance with the first and second gate signals. Even when inversion points of the first or second gate signal deviate from edges of the clock signal, no glitches result.

Abstract: In a conventional gated clock generating circuit, different signal delay times are produced depending on the arrangement of interconnection of circuit elements, often causing glitches. To avoid this, a gated clock generating circuit of the invention has a circuit that generates a first gate signal having inversion points synchronous with edges of a continuously pulsating clock signal, a circuit that generates a second gate signal deviated by half the period of the clock signal relative to the first gate signal, and a circuit that turns on and off the output of the clock signal in accordance with the first and second gate signals. Even when inversion points of the first or second gate signal deviate from edges of the clock signal, no glitches result.