Abstract: A pixel of a light-emitting display device includes a capacitor, a first transistor, a second transistor including a gate receiving a gate writing signal, a third transistor including a gate receiving a scan signal, a fourth transistor including a gate receiving a gate initialization signal, a fifth transistor including a gate receiving a first emission signal, a sixth transistor including a gate receiving a second emission signal, and a light-emitting diode. The scan signal and the gate writing signal may be provided at a first frequency, and the first emission signal, the second emission signal and the gate initialization signal may be provided at a second frequency higher than the first frequency.

Abstract: A display device includes a first pixel driver connected to a sweep line, the first pixel driver generating a control current based on a first data voltage, a second pixel driver connected to a scan control line, the second pixel driver generating a driving current based on a second data voltage and controlling a period for which the driving current flows, based on the control current, and a light-emitting element connected to the second pixel driver to receive the driving current. The first pixel driver includes a first transistor generating the control current based on the first data voltage, a second transistor providing the first data voltage to a first electrode of the first transistor based on a scan write signal, and a first capacitor including a first capacitor electrode connected to a gate electrode of the first transistor, and a second capacitor electrode connected to the sweep line.

Abstract: A light emitting display device includes a pixel circuit unit, a data distribution unit, a plurality of signal generating units, a unit light emitting diode, and a dummy opening. The pixel circuit unit is configured to generate an output current. The data distribution unit is configured to apply a data voltage to the pixel circuit unit through a data line. The plurality of signal generating units are respectively configured to apply a scan signal and a light emission control signal to the pixel circuit unit through a plurality of signal lines. The unit light emitting diode is configured to receive the output current of the pixel circuit unit and is attached to the pixel circuit unit. The dummy opening is formed in the region where the pixel circuit unit, the data distribution unit, and a plurality of signal generating units are not positioned.

Abstract: A display device includes a display area which displays an image, and a non-display area disposed around the display area and including a pad part. The display area includes pixels of a first pixel row which are pixels arranged in a first direction along the first pixel row, pixels of a second pixel row, which are pixels arranged in the first direction along the second pixel row next to the first pixel row, and pixel circuits of a first circuit row which are pixel circuits arranged in the first direction along the first circuit row, where the pixel circuits of the first circuit row are electrically connected to the pixels of the first pixel row, respectively. The first pixel row and the first circuit row are spaced apart from each other with the second pixel row interposed therebetween.

Abstract: A display device includes a pixel unit including first pixels disposed in a first area and second pixels disposed in a second area, an emission driver configured to sequentially supply emission signals of a turn-off level to the first pixels and the second pixels based on a first start signal, a first clock signal, and a second clock signal, and a first scan driver configured to sequentially supply first scan signals of a turn-on level to the first pixels based on a second start signal, the first clock signal, and the second clock signal, and sequentially supply the first scan signals of the turn-on level to the second pixels based on a third start signal, the first clock signal, and the second clock signal.

Abstract: A light emitting display device includes a pixel circuit unit, a data distribution unit, a plurality of signal generating units, a unit light emitting diode, and a dummy opening. The pixel circuit unit is configured to generate an output current. The data distribution unit is configured to apply a data voltage to the pixel circuit unit through a data line. The plurality of signal generating units are respectively configured to apply a scan signal and a light emission control signal to the pixel circuit unit through a plurality of signal lines. The unit light emitting diode is configured to receive the output current of the pixel circuit unit and is attached to the pixel circuit unit. The dummy opening is formed in the region where the pixel circuit unit, the data distribution unit, and a plurality of signal generating units are not positioned.

Abstract: A display device comprises a substrate, a semiconductor layer thereon, a first insulating layer on the semiconductor layer, a first conductive layer on the first insulating layer and including a first electrode pattern, a second insulating layer on the first insulating layer and including first and second conductive patterns, a third insulating layer on the second conductive layer, and a display element layer on the third insulating layer and including a first pixel electrode connected to the first conductive pattern through a first via hole, a second pixel electrode connected to the second conductive pattern through a second via hole, and a micro light-emitting element between the pixel electrodes, the first conductive pattern contacting the semiconductor layer through a first contact hole and the first electrode pattern through a second contact hole, and the second conductive pattern overlapping the first electrode pattern to form a first capacitor therewith.

Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.

Abstract: A display device includes PAM data lines receiving PAM and PWM data voltages, and sub-pixels connected to the PAM and PWM data lines. A sub-pixel includes a light emitting element, a first pixel driver to supply a control current according to one of the PAM data voltages to a node, a second pixel driver to generate a driving current according to one of the PWM data voltages, and a third pixel driver to adjust a period during which the driving current is supplied to the light emitting element according to a voltage of the node. A peak current value of the driving current when the sub-pixel emits a light corresponding to a low gray level region is smaller than a peak current value of the driving current when the sub-pixel emits a light corresponding to a high gray level region higher than the low gray level region.

Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.

Abstract: A display device comprises a substrate, a semiconductor layer thereon, a first insulating layer on the semiconductor layer, a first conductive layer on the first insulating layer and including a first electrode pattern, a second insulating layer on the first insulating layer and including first and second conductive patterns, a third insulating layer on the second conductive layer, and a display element layer on the third insulating layer and including a first pixel electrode connected to the first conductive pattern through a first via hole, a second pixel electrode connected to the second conductive pattern through a second via hole, and a micro light-emitting element between the pixel electrodes, the first conductive pattern contacting the semiconductor layer through a first contact hole and the first electrode pattern through a second contact hole, and the second conductive pattern overlapping the first electrode pattern to form a first capacitor therewith.

Abstract: A display device includes a scan write line, a PWM emission line, a PAM emission line, a sweep signal line, a first data line, a second data line, and a subpixel connected thereto, and including a light emitting element, a first pixel driver to supply a control current to a node according to the first data voltage in response to the PWM emission signal, a second pixel driver to generate a driving current according to the second data voltage in response to the PWM emission signal, and a third pixel driver to supply the driving current to the light emitting element according to the PAM emission signal and a voltage of the node, wherein the PWM emission signal includes a plurality of PWM pulses, the PAM emission signal includes a plurality of PAM pulses, and a number of the PWM pulses is greater than a number of the PAM pulses.

Abstract: A display device includes connection lines, pulse amplitude modulation (PAM) data lines configured to receive pulse width modulation (PWM) data voltages, PWM data lines configured to receive the PWM data voltages, a first connection control line configured to receive a first connection control signal, a second connection control line configured to receive a second connection control signal, subpixels connected to the PWM data lines and the PAM data lines, and a first demultiplexer (demux) unit configured to connect the connection lines to the PAM data lines or to the PWM data lines according to the first connection control signal and the second connection control signal.

Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.

Abstract: A display device including: a first transistor configured to control a control current based on a voltage of a first node; a second transistor configured to electrically connect a second node that is a first electrode of the first transistor to a first data line in response to a scan write signal; a third transistor configured to control a driving current based on a voltage of a third node; a fourth transistor configured to electrically connect a fourth node that is a first electrode of the third transistor to a second data line in response to the scan write signal; a fifth transistor configured to control the driving current based on a voltage of a fifth node having received the control current; and a light emitting element configured to receive the driving current, wherein the fifth transistor is of a different type from that of the first to fourth transistors.

Abstract: A display device includes PAM data lines receiving PAM and PWM data voltages, and sub-pixels connected to the PAM and PWM data lines. A sub-pixel includes a light emitting element, a first pixel driver to supply a control current according to one of the PAM data voltages to a node, a second pixel driver to generate a driving current according to one of the PWM data voltages, and a third pixel driver to adjust a period during which the driving current is supplied to the light emitting element according to a voltage of the node. A peak current value of the driving current when the sub-pixel emits a light corresponding to a low gray level region is smaller than a peak current value of the driving current when the sub-pixel emits a light corresponding to a high gray level region higher than the low gray level region.

Abstract: A sweep signal driver includes: a kth stage to output a kth emission signal to a kth emission line, and a kth sweep signal to a kth sweep signal line, the kth stage including: first, second, and third pull-up nodes; a node connection circuit between the first pull-up node and the second pull-up node, and between the first pull-up node and the third pull-up node; a first output circuit to output a sweep clock signal of a sweep clock terminal to a first output terminal connected to the kth sweep signal line when the third pull-up node has a gate-on voltage; and a second output circuit to output a gate-on voltage to a second output terminal connected to the kth emission line when the second pull-up node has a gate-on voltage. A pulse of the kth sweep signal linearly changes from a gate-off voltage to the gate-on voltage.

Abstract: A display device includes a scan write line, a PWM emission line, a PAM emission line, a sweep signal line, a first data line, a second data line, and a subpixel connected thereto, and including a light emitting element, a first pixel driver to supply a control current to a node according to the first data voltage in response to the PWM emission signal, a second pixel driver to generate a driving current according to the second data voltage in response to the PWM emission signal, and a third pixel driver to supply the driving current to the light emitting element according to the PAM emission signal and a voltage of the node, wherein the PWM emission signal includes a plurality of PWM pulses, the PAM emission signal includes a plurality of PAM pulses, and a number of the PWM pulses is greater than a number of the PAM pulses.

Abstract: A display device includes a first pixel driver connected to a sweep line, the first pixel driver generating a control current based on a first data voltage, a second pixel driver connected to a scan control line, the second pixel driver generating a driving current based on a second data voltage and controlling a period for which the driving current flows, based on the control current, and a light-emitting element connected to the second pixel driver to receive the driving current. The first pixel driver includes a first transistor generating the control current based on the first data voltage, a second transistor providing the first data voltage to a first electrode of the first transistor based on a scan write signal, and a first capacitor including a first capacitor electrode connected to a gate electrode of the first transistor, and a second capacitor electrode connected to the sweep line.

Abstract: A display device includes connection lines, pulse amplitude modulation (PAM) data lines configured to receive pulse width modulation (PWM) data voltages, PWM data lines configured to receive the PWM data voltages, a first connection control line configured to receive a first connection control signal, a second connection control line configured to receive a second connection control signal, subpixels connected to the PWM data lines and the PAM data lines, and a first demultiplexer (demux) unit configured to connect the connection lines to the PAM data lines or to the PWM data lines according to the first connection control signal and the second connection control signal.