Abstract: A semiconductor device includes a substrate including an upper surface and a lower surface that are opposite to each other in a first direction, an active pattern which is on the upper surface of the substrate and extends in a second direction, a gate electrode which is on the active pattern and extends in a third direction, a first source/drain pattern which is connected to the active pattern on the upper surface of the substrate, and includes a lower epitaxial region and an upper epitaxial region, the upper epitaxial region including an epitaxial recess, and the lower epitaxial region being inside the epitaxial recess, a first source/drain contact, which is connected to the first source/drain pattern and extends into the substrate, and a contact silicide layer, which is between the first source/drain contact and the first source/drain pattern and contacts the lower epitaxial region.

Abstract: A semiconductor device includes a gate structure including a gate electrode on a substrate. A source/drain pattern is on the substrate and positioned on a side surface of the gate electrode. A source/drain contact is on the source/drain pattern. A first conductive pad is on the source/drain contact. A second conductive pad is on the gate structure. A via plug penetrates the first conductive pad and is connected to the source/drain contact. A gate contact penetrates the second conductive pad and is connected to the gate electrode. A portion of the via plug protrudes from the first conductive pad. A portion of the gate contact protrudes from the second conductive pad. A height from an upper surface of the gate structure to an upper surface of the via plug is equal to a height from the upper surface of the gate structure to an upper surface of the gate contact.

Abstract: A semiconductor device may include a backside wiring line in a first backside interlayer insulating film, a fin-type pattern on the backside wiring line, a second backside interlayer insulating film between the fin-type pattern and the first backside interlayer insulating film, a gate electrode on the fin-type pattern, a first source/drain pattern on a side of the gate electrode, and a backside source/drain contact in a backside contact hole defined by the fin-type pattern and the second backside interlayer insulating film. The backside source/drain contact may connect the backside wiring line and the first source/drain pattern. The backside source/drain contact may include an upper pattern and a lower pattern. The upper pattern may be between the lower pattern and the first source/drain pattern, and may fill at least a portion of the first backside contact hole. The upper pattern may have a single conductive film structure.

Abstract: A semiconductor device includes a back interlayer insulating film, a back wiring line in the back interlayer insulating film, the back wiring line including a first surface and a second surface opposite the first surface in a first direction, a fin-type pattern on the first surface of the back wiring line and extending in a second direction, a gate electrode on the fin-type pattern and extending in a third direction, a first source/drain pattern on a first side of the gate electrode, the first source/drain pattern including a bottom surface contacting the fin-type pattern, a back source/drain contact in the fin-type pattern and connected to the first surface of the back wiring line, and a contact insulating liner between the fin-type pattern and the back source/drain contact, the contact insulating liner extending along at least a portion of side walls of the back source/drain contact.

Abstract: The present disclosure relates to a polyester-based resin composition and a molded article manufactured using the same. More particularly, the present disclosure relates to a polyester-based resin composition including 93 to 99.5% by weight of a polybutylene terephthalate resin; 0.1 to 3% by weight of a polar group-containing lubricant; and 0.1 to 2% by weight of an antioxidant and a molded article manufactured using the polyester-based resin composition.

Abstract: A semiconductor device may include gate structures spaced apart from each other on an active pattern, where each of the gate structures includes gate spacers on sidewalls of a gate electrode, source/drain patterns between the gate structures, source/drain contacts on the source/drain patterns, and contact silicide films between the source/drain contacts and the source/drain patterns. Outer surfaces of the contact silicide films may contact the source/drain patterns and inner surfaces of the contact silicide films may contact the source/drain contacts. A width in a first direction of the contact silicide films may be maximum at the uppermost portions of outer surfaces of the contact silicide films. Parts of the outer surfaces of the contact silicide films may contact the gate spacers. The width in the first direction of the uppermost portions of the contact silicide films may be equal to a width in the first direction of the source/drain contacts.

Abstract: A semiconductor device includes an active pattern extending in a first direction, a plurality of gate structures on the active pattern spaced in the first direction, and including a gate electrode extending in a second direction, a source/drain pattern between adjacent gate structures, a silicide mask pattern on the source/drain pattern, an upper surface of the silicide mask pattern being lower than an upper surface of the gate electrode, a source/drain contact on the source/drain pattern connected to the source/drain pattern, and a contact silicide film between the source/drain contact and the source/drain pattern in contact with a bottom surface of the silicide mask pattern, wherein a height from a lowermost part of the source/drain pattern to a lowermost part of the source/drain contact is smaller than a height from the lowermost part of the source/drain pattern to the bottom surface of the silicide mask pattern.

Abstract: A semiconductor device includes a substrate including an upper surface and a lower surface that are opposite to each other in a first direction, an active pattern which is on the upper surface of the substrate and extends in a second direction, a gate electrode which is on the active pattern and extends in a third direction, a first source/drain pattern which is connected to the active pattern on the upper surface of the substrate, and includes a lower epitaxial region and an upper epitaxial region, the upper epitaxial region including an epitaxial recess, and the lower epitaxial region being inside the epitaxial recess, a first source/drain contact, which is connected to the first source/drain pattern and extends into the substrate, and a contact silicide layer, which is between the first source/drain contact and the first source/drain pattern and contacts the lower epitaxial region.

Abstract: A semiconductor device includes an active pattern extending in a first direction, a plurality of gate structures on the active pattern spaced in the first direction, and including a gate electrode extending in a second direction, a source/drain pattern between adjacent gate structures, a silicide mask pattern on the source/drain pattern, an upper surface of the silicide mask pattern being lower than an upper surface of the gate electrode, a source/drain contact on the source/drain pattern connected to the source/drain pattern, and a contact silicide film between the source/drain contact and the source/drain pattern in contact with a bottom surface of the silicide mask pattern, wherein a height from a lowermost part of the source/drain pattern to a lowermost part of the source/drain contact is smaller than a height from the lowermost part of the source/drain pattern to the bottom surface of the silicide mask pattern.

Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.

Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.

Abstract: The present disclosure relates to a polyester-based resin composition and a molded article manufactured using the same. More particularly, the present disclosure relates to a polyester-based resin composition including 93 to 99.5% by weight of a polybutylene terephthalate resin; 0.1 to 3% by weight of a polar group-containing lubricant; and 0.1 to 2% by weight of an antioxidant and a molded article manufactured using the polyester-based resin composition.

Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a substrate chuck, a shower head structure over the substrate chuck, and a gas distribution apparatus connected to the shower head structure. The gas distribution apparatus includes a dispersion container including a first dispersion space and a gas inlet section on the dispersion container. The gas inlet section includes a first inlet pipe including a first inlet path fluidly connected to the first dispersion space and a second inlet pipe including a second inlet path fluidly connected to the first dispersion space. The second inlet pipe surrounds at least a portion of a sidewall of the first inlet pipe.

Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a substrate chuck, a shower head structure over the substrate chuck, and a gas distribution apparatus connected to the shower head structure. The gas distribution apparatus includes a dispersion container including a first dispersion space and a gas inlet section on the dispersion container. The gas inlet section includes a first inlet pipe including a first inlet path fluidly connected to the first dispersion space and a second inlet pipe including a second inlet path fluidly connected to the first dispersion space. The second inlet pipe surrounds at least a portion of a sidewall of the first inlet pipe.

Abstract: The present invention relates to a method for generating a reference signal to drive a display apparatus. A method according to the present invention may comprise generating a reference signal having a training pattern being repeated with a periodicity of two clock terms (CTs); and transmitting the reference signal to a phase locked loop (PLL). Each CT has a single embedded clock bit (CB) and a plurality of data bits, and the reference signal has a rising edge at a start point of a first CB corresponding to a first unit interval (UI) of a first CT, and a rising edge at an end point of a second CB corresponding to a first UI of a second CT. According to exemplary embodiments of the present disclosure, energy consumption and EMI effects can be remarkably reduced, and a complexity of PLL can be reduced.

Abstract: The present invention relates to a method for generating a reference signal to drive a display apparatus. A method according to the present invention may comprise generating a reference signal having a training pattern being repeated with a periodicity of two clock terms (CTs); and transmitting the reference signal to a phase locked loop (PLL). Each CT has a single embedded clock bit (CB) and a plurality of data bits, and the reference signal has a rising edge at a start point of a first CB corresponding to a first unit interval (UI) of a first CT, and a rising edge at an end point of a second CB corresponding to a first UI of a second CT. According to exemplary embodiments of the present disclosure, energy consumption and EMI effects can be remarkably reduced, and a complexity of PLL can be reduced.