Patents by Inventor Junki Taniguchi
Junki Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240116075Abstract: A selective film deposition method includes exposing a substrate having a structure on which a first surface region containing a metal element and a second surface region containing a nonmetal inorganic material are both exposed, to a solution containing an organic substance represented by formula (1) shown below and a solvent to deposit a film of the organic substance on the first surface region selectively over the second surface region: R1(X)m (1) wherein R1 is a C4-C100 hydrocarbon group optionally containing a heteroatom or a halogen atom, and m hydrogen atoms of the hydrocarbon group are replaced with X; X is —PO3(R2)2, —O—PO3(R2)2, —CO2R2, —SR2, or —SSR1; each R2 is a hydrogen atom or a C1-C6 alkyl group; and m is a positive integer, and m/r is 0.01 to 0.25 where r is the number of carbons of the hydrocarbon group.Type: ApplicationFiled: January 28, 2022Publication date: April 11, 2024Applicant: CENTRAL GLASS COMPANY, LIMITEDInventors: Takuya OKADA, Junki YAMAMOTO, Takahisa TANIGUCHI, Kazuki YOSHIURA, Katsuya KONDO, Soichi KUMON, Tatsuo MIYAZAKI
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Patent number: 11552626Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.Type: GrantFiled: August 6, 2021Date of Patent: January 10, 2023Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Publication number: 20210367587Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.Type: ApplicationFiled: August 6, 2021Publication date: November 25, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Tetsuya Arai, Junki Taniguchi
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Patent number: 11088681Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.Type: GrantFiled: March 19, 2019Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Patent number: 11087802Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.Type: GrantFiled: March 25, 2019Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Patent number: 11057038Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.Type: GrantFiled: October 17, 2019Date of Patent: July 6, 2021Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Shuichi Tsukada, Junki Taniguchi
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Patent number: 11031054Abstract: Apparatuses and methods for pre-emphasis control are described. An example apparatus includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal. The pull-down circuit is configured to receive a pull-down activation signal and drive a data terminal to a pull-down voltage responsive to an active pull-down data activation signal. The example apparatus further includes a pull-up pre-emphasis circuit that includes a pre-emphasis timing control circuit configured to provide a timing control signal, and further includes a pull-up logic circuit. A pull-up pre-emphasis control signal based on pull-up data activation signal is provided to control providing pull-up pre-emphasis for greater than one unit interval of data when the pull-up data activation signal remains active for greater than one unit interval.Type: GrantFiled: January 22, 2020Date of Patent: June 8, 2021Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Publication number: 20200304114Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level, and a second circuit configured to drive the first signal node to other of the first and second logic levels.Type: ApplicationFiled: March 19, 2019Publication date: September 24, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: TETSUYA ARAI, JUNKI TANIGUCHI
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Patent number: 10777257Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.Type: GrantFiled: December 9, 2019Date of Patent: September 15, 2020Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Patent number: 10726884Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.Type: GrantFiled: June 13, 2019Date of Patent: July 28, 2020Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Publication number: 20200052698Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.Type: ApplicationFiled: October 17, 2019Publication date: February 13, 2020Applicant: Micron Technology, Inc.Inventors: Tetsuya Arai, Shuichi Tsukada, Junki Taniguchi
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Patent number: 10529412Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.Type: GrantFiled: April 9, 2019Date of Patent: January 7, 2020Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Patent number: 10511306Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.Type: GrantFiled: July 26, 2016Date of Patent: December 17, 2019Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Shuichi Tsukada, Junki Taniguchi
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Publication number: 20190295609Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.Type: ApplicationFiled: June 13, 2019Publication date: September 26, 2019Applicant: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Publication number: 20190221245Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Applicant: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Patent number: 10339984Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.Type: GrantFiled: June 4, 2018Date of Patent: July 2, 2019Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Patent number: 10269395Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.Type: GrantFiled: May 6, 2015Date of Patent: April 23, 2019Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Publication number: 20180286467Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.Type: ApplicationFiled: June 4, 2018Publication date: October 4, 2018Applicant: Micron Technology, Inc.Inventors: TETSUYA ARAI, Junki Taniguchi
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Patent number: 10026457Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.Type: GrantFiled: April 18, 2017Date of Patent: July 17, 2018Assignee: Micron Technology, Inc.Inventors: Tetsuya Arai, Junki Taniguchi
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Publication number: 20170353183Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.Type: ApplicationFiled: July 26, 2016Publication date: December 7, 2017Applicant: Micron Technology, Inc.Inventors: Tetsuya Arai, Shuichi Tsukada, Junki Taniguchi