Patents by Inventor Junko Azami

Junko Azami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8604588
    Abstract: A semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: December 10, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Kenichiro Kusano, Junko Azami
  • Publication number: 20110204481
    Abstract: The present invention provides a semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween.
    Type: Application
    Filed: February 22, 2011
    Publication date: August 25, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Kenichiro Kusano, Junko Azami
  • Patent number: 6921944
    Abstract: A semiconductor device has a first semiconductor element and a second semiconductor element formed on a semiconductor substrate. The second semiconductor element is operated with a first voltage. The first semiconductor element is operated with a second voltage that is higher than the first voltage. The pairs of impurity regions of the first and second semiconductor elements respectively have first impurity areas and second impurity areas. Each of the first impurity areas have a predetermined impurity concentration and a conductivity type opposite to a conductivity type of the semiconductor substrate. The second impurity areas extend toward their corresponding gates from the first impurity areas. The second impurity areas have a same conductivity type as the first impurity areas and an impurity concentration lower than the concentration of the first impurity area.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: July 26, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroshi Aoki, Junko Azami
  • Publication number: 20030006460
    Abstract: A semiconductor device has a first semiconductor element and a second semiconductor element formed on a semiconductor substrate. The second semiconductor element is operated with a first voltage. The first semiconductor element is operated with a second voltage that is higher than the first voltage. The pairs of impurity regions of the first and second semiconductor elements respectively have first impurity areas and second impurity areas. Each of the first impurity areas indicative of a predetermined impurity concentration by an impurity indicative of a conductivity type opposite to a conductivity type of the semiconductor substrate. The second impurity areas extend toward their corresponding gates from the first impurity areas. The second impurity areas indicate the same conductivity type as the first impurity areas and are indicative of an impurity concentration lower than the concentration of the first impurity area.
    Type: Application
    Filed: May 23, 2002
    Publication date: January 9, 2003
    Inventors: Hiroshi Aoki, Junko Azami
  • Patent number: 6096600
    Abstract: The phosphorus concentration of an upper electrode and the phosphorus concentration of a lower electrode can be made equally high without loss of adhesion between the polysilicon and a metallic layer. It includes a step of forming a stacked layer structure consisting of: a lower electrode layer provided on an underlay, a dielectric layer provided on this lower electrode layer, and an upper electrode layer consisting of an impurity-doped layer and a metallic layer successively provided on this dielectric layer, and a step of doping the metallic layer with the same impurity as the impurity in the impurity-doped layer prior to heat treatment of the stacked layer structure.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: August 1, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Junko Azami