Patents by Inventor Junko Honma

Junko Honma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device
    Patent number: 7911027
    Abstract: It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Mitsumi Itoh, Masatoshi Sawada, Junko Honma, Kenji Shimazaki, Hiroyuki Tsujikawa, Hiroshi Benno
  • Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device
    Patent number: 7307333
    Abstract: It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: December 11, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsumi Itoh, Masatoshi Sawada, Junko Honma, Kenji Shimazaki, Hiroyuki Tsujikawa, Hiroshi Benno
  • Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device
    Publication number: 20070187777
    Abstract: It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
    Type: Application
    Filed: April 10, 2007
    Publication date: August 16, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsumi Itoh, Masatoshi Sawada, Junko Honma, Kenji Shimazaki, Hiroyuki Tsujikawa, Hiroshi Benno
  • Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device
    Publication number: 20050017320
    Abstract: It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
    Type: Application
    Filed: November 21, 2002
    Publication date: January 27, 2005
    Inventors: Mitsumi Itoh, Masatoshi Sawada, Junko Honma, Kenji Shimazaki, Hiroyuki Tsujikawa, Hiroshi Benno