Patents by Inventor Junko Kimura
Junko Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10630067Abstract: A semiconductor device is provided for measuring a voltage of each of plural unit cells series-coupled in multi-stage and configuring an assembled battery. The semiconductor device includes two terminals coupled to two nodes which are electrodes of a unit cell and coupled with other unit cells, and a voltage measurement circuit which measures the inter-terminal voltage between the two terminals. The device also includes a down-convert level shifter circuit which converts the inter-terminal voltage into a low-potential-side inter-terminal voltage based on a ground potential, and a comparator circuit which compares the converted low-potential-side inter-terminal voltage with a predetermined reference voltage.Type: GrantFiled: July 6, 2017Date of Patent: April 21, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshitaka Muramoto, Junko Kimura, Hirohiko Hayakawa
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Publication number: 20170302069Abstract: A semiconductor device is provided for measuring a voltage of each of plural unit cells series-coupled in multi-stage and configuring an assembled battery. The semiconductor device includes two terminals coupled to two nodes which are electrodes of a unit cell and coupled with other unit cells, and a voltage measurement circuit which measures the inter-terminal voltage between the two terminals. The device also includes a down-convert level shifter circuit which converts the inter-terminal voltage into a low-potential-side inter-terminal voltage based on a ground potential, and a comparator circuit which compares the converted low-potential-side inter-terminal voltage with a predetermined reference voltage.Type: ApplicationFiled: July 6, 2017Publication date: October 19, 2017Inventors: Yoshitaka MURAMOTO, Junko KIMURA, Hirohiko HAYAKAWA
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Patent number: 9735567Abstract: A semiconductor device is provided for measuring a voltage of each of plural unit cells series-coupled in multi-stage and configuring an assembled battery. The semiconductor device includes two terminals coupled to two nodes which are electrodes of a unit cell and coupled with other unit cells, and a voltage measurement circuit which measures the inter-terminal voltage between the two terminals. The device also includes a down-convert level shifter circuit which converts the inter-terminal voltage into a low-potential-side inter-terminal voltage based on a ground potential, and a comparator circuit which compares the converted low-potential-side inter-terminal voltage with a predetermined reference voltage.Type: GrantFiled: August 16, 2013Date of Patent: August 15, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshitaka Muramoto, Junko Kimura, Hirohiko Hayakawa
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Patent number: 9564765Abstract: In battery voltage monitoring ICs for measuring voltages of unit cells of an assembled battery, communication with a system control unit is realized in consideration of fail-safe. The system control unit and the battery voltage monitoring ICs are coupled to each other by a communication path using a daisy chain. Each battery voltage monitoring IC has a placement setting pin designating, by a binary code, a unit cell group to which the IC is coupled, in the unit cell groups. When it is detected that the Hamming distance between the code indicative of coupling to a group of the highest potential or a group of the lowest potential and a state actually set in the placement setting pin is 1, some failure such as line disconnection, short-circuit, or the like in the placement setting pins is detected, and the communication path is interrupted.Type: GrantFiled: September 10, 2012Date of Patent: February 7, 2017Assignee: Renesas Electronics CorporationInventors: Akiko Fukute, Ryosuke Enomoto, Junko Kimura, Toshitaka Ukai
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Publication number: 20160035706Abstract: A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.Type: ApplicationFiled: October 13, 2015Publication date: February 4, 2016Inventors: Mikihiko Komatsu, Takao Hidaka, Junko Kimura
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Patent number: 9209113Abstract: A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.Type: GrantFiled: October 20, 2014Date of Patent: December 8, 2015Assignee: Renesas Electronics CorporationInventors: Mikihiko Komatsu, Takao Hidaka, Junko Kimura
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Publication number: 20150270727Abstract: In battery voltage monitoring ICs for measuring voltages of unit cells of an assembled battery, communication with a system control unit is realized in consideration of fail-safe. The system control unit and the battery voltage monitoring ICs are coupled to each other by a communication path using a daisy chain. Each battery voltage monitoring IC has a placement setting pin designating, by a binary code, a unit cell group to which the IC is coupled, in the unit cell groups. When it is detected that the Hamming distance between the code indicative of coupling to a group of the highest potential or a group of the lowest potential and a state actually set in the placement setting pin is 1, some failure such as line disconnection, short-circuit, or the like in the placement setting pins is detected, and the communication path is interrupted.Type: ApplicationFiled: September 10, 2012Publication date: September 24, 2015Inventors: Akiko Fukute, Ryosuke Enomoto, Junko Kimura, Toshitaka Ukai
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Publication number: 20150102501Abstract: A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.Type: ApplicationFiled: October 20, 2014Publication date: April 16, 2015Inventors: Mikihiko Komatsu, Takao Hidaka, Junko Kimura
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Patent number: 9000574Abstract: A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.Type: GrantFiled: February 23, 2012Date of Patent: April 7, 2015Assignee: Renesas Electronics CorporationInventors: Mikihiko Komatsu, Takao Hidaka, Junko Kimura
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Publication number: 20140055896Abstract: A semiconductor device is provided for measuring a voltage of each of plural unit cells series-coupled in multi-stage and configuring an assembled battery. The semiconductor device includes two terminals coupled to two nodes which are electrodes of a unit cell and coupled with other unit cells, and a voltage measurement circuit which measures the inter-terminal voltage between the two terminals. The device also includes a down-convert level shifter circuit which converts the inter-terminal voltage into a low-potential-side inter-terminal voltage based on a ground potential, and a comparator circuit which compares the converted low-potential-side inter-terminal voltage with a predetermined reference voltage.Type: ApplicationFiled: August 16, 2013Publication date: February 27, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshitaka MURAMOTO, Junko KIMURA, Hirohiko HAYAKAWA
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Publication number: 20120146245Abstract: A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.Type: ApplicationFiled: February 23, 2012Publication date: June 14, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Mikihiko Komatsu, Takao Hidaka, Junko Kimura
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Patent number: 8134228Abstract: A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires respectively. In another example, fourth and fifth pad are disposed along a side different form a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.Type: GrantFiled: June 23, 2009Date of Patent: March 13, 2012Assignee: Renesas Electronics CorporationInventors: Mikihiko Komatsu, Takao Hidaka, Junko Kimura
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Publication number: 20100072604Abstract: To provide a technique of supplying a voltage generated in any of a plurality of semiconductor chips to the other chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. In an example of the main technique, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.Type: ApplicationFiled: June 23, 2009Publication date: March 25, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Mikihiko KOMATSU, Takao HIDAKA, Junko KIMURA
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Patent number: 7492210Abstract: A first switch circuit includes first and second N-type MOSFETs. A second switch circuit includes third and fourth N-type MOSFETs. A control signal is input to a first inverter and a third inverter, the output of the first inverter input to a second inverter and the gate of the fourth MOSFET, the output of the second inverter input to the gate of the first MOSFET, the output of the third inverter input to a fourth inverter and the gate of the third MOSFET, the output of the fourth inverter input to the gate of the second MOSFET. A first input voltage is connected to the source of the second MOSFET and the sources of N-type MOSFETS in the third and fourth inverters. A second input voltage is connected the source of the fourth MOSFET and the sources of N-type MOSFETS in the first and second inverters.Type: GrantFiled: December 21, 2006Date of Patent: February 17, 2009Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Manufacturing Co., Ltd.Inventors: Toshiyuki Imai, Junko Kimura
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Publication number: 20070152731Abstract: A voltage selection circuit is disclosed which comprises: a first through a fourth inverters; a first switch circuit including a first MOSFET of N type and a second MOSFET of N type, respective drains thereof being connected in common; and a second switch circuit including a third MOSFET of N type and a fourth MOSFET of N type, respective drains thereof being connected in common, a common drive voltage being input to the first through fourth inverters, a control signal being input to the first inverter and the third inverter, the output of the first inverter being input to the second inverter and the gate of the fourth MOSFET, the output of the second inverter being input to the gate of the first MOSFET, the output of the third inverter being input to the fourth inverter and the gate of the third MOSFET, the output of the fourth inverter being input to the gate of the second MOSFET, a first input voltage selected depending on the control signal being input to the source of the second MOSFET, a second input voType: ApplicationFiled: December 21, 2006Publication date: July 5, 2007Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Toshiyuki Imai, Junko Kimura
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Patent number: 5694173Abstract: A video data arranging method includes the steps of providing a normal bit stream region in which normal playback block codes for normal playback of prescribed picture blocks and special playback block codes for special playback of prescribed picture blocks can be arranged, and providing a extension bit stream region for arranging block codes which are not arranged in the normal bit stream region out of the normal playback block codes and the special playback block codes when there are the normal playback block codes and the special playback block codes for prescribed picture blocks, and video data encoding/decoding apparatus suited for the method.Type: GrantFiled: December 29, 1994Date of Patent: December 2, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Junko Kimura, Kenji Shimoda
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Patent number: 5289190Abstract: The present invention relates to a recording/reproducing apparatus which records an effective transmit information signal on a recording medium in a high-efficiency coded form and decodes the high-efficiency coded signal read from the recording medium to recover the original information signal. At the time of recording or dubbing of the recovered information signal on another recording medium, the information signal, a control signal indicating whether or not the information signal has been subjected to high-efficiency coding and decoding processes and a specific signal indicating a specific value used in the high-efficiency coding and decoding processes when the information signal has been subjected to the high-efficiency coding and decoding processes are transmitted, thereby preventing the deterioration of data due to the high-efficiency coding.Type: GrantFiled: December 27, 1991Date of Patent: February 22, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Shimoda, Junko Kimura
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Patent number: 5216712Abstract: A recording apparatus for recording a digital data, which includes an orthogonal transform unit for transforming the time axis of the digital data to the frequency axis on a block-by-block basis, a conversion circuit for converting the digital data from the orthogonal transform means to a digital recording data and a circuit for causing the conversion circuit to convert the digital data to a recording data which is substantially impossible to be restored to the original digital data.Type: GrantFiled: December 24, 1991Date of Patent: June 1, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Shimoda, Junko Kimura
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Patent number: 5161031Abstract: A video tape recorder including a divider for sampling video data input into the video tape recorder and dividing the video data into N sub-picture data elements, where N is an integer equal to or larger than 2, a recorder head for recording the N sub-picture data elements on a recording medium, a data reproducing circuit for reproducing the first through M-th of the recorded sub-picture data elements, where M is an integer such that 1.ltoreq.M<N, a circuit for distributing the first through M-th sub-picture elements reproduced by the reproducing circuit, and a device for displaying the data elements distributed by the distributing circuit.Type: GrantFiled: March 21, 1990Date of Patent: November 3, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Junko Kimura, Shigeo Tanaka