Patents by Inventor Junko Morikawa

Junko Morikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12335611
    Abstract: A first image capturing unit (203 to 205) configured to capture an image using a lens placed on a first surface, a second image capturing unit (201 and 202) configured to capture an image using a lens placed on a second surface, the second image capturing unit being configured to switch to first image capturing using a first lens and second image capturing using a second lens with a wider angle than an angle of view of the first lens, and a control unit configured to perform control to, during the image capturing by the second image capturing unit, in response to a user operation for changing from a still image capturing mode to a moving image capturing mode, switch to the moving image capturing mode and also switch from the first image capturing using the first lens to the second image capturing using the second lens, are included.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: June 17, 2025
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshihiro Funatsu, Koki Kitaya, Junko Morikawa
  • Patent number: 12328490
    Abstract: An electronic device having a first surface on which a first lens and a second lens with a wider angle than the first lens is arranged and a second surface on which at least a third lens is arranged, the electronic device comprising control means for controlling a captured image of the first lens to be displayed in response to issuing an instruction to display a captured image of a lens on the first surface, and controlling a captured image at a second field angle wider than the first field angle to be displayed in response to issuing an instruction to display a captured image of a lens on the second surface.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: June 10, 2025
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryo Takahashi, Junko Morikawa
  • Patent number: 12267587
    Abstract: An electronic apparatus including a first lens and a second lens at a first side, the second lens having a angle of view different from that of the first lens, includes a switching unit configured to switch first imaging via the first lens and second imaging via the second lens, and a control unit configured to control display of items corresponding to a plurality of respective imaging modes, wherein the control unit is configured to, in a case where the second imaging is being performed, control display of a first item and a second item in different display modes, the first item corresponding to an imaging mode that enables the first imaging and the second imaging, the second item corresponding to an imaging mode that enables the first imaging and disables the second imaging.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: April 1, 2025
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Ogawa, Junko Morikawa, Keiko Yamada
  • Patent number: 12035066
    Abstract: An image providing system capable of quickly providing a plurality of different cropped images is disclosed. The image providing system acquires position information about a position of a user designated by the user. The image providing system determines a range of an image that was captured by an image capturing unit, the range corresponding to the position information as a cropping range, before the image capturing unit starts a series of image capturing in which the image capturing unit captures a plurality of images. After the series of image capturing is started, the system applies cropping that cuts out a part of a captured image based on the cropping range. During the series of image capturing, the system provides a cropped image to which the cropping has been applied in a way in which a user can obtain the cropped image.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: July 9, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tomonobu Hiraishi, Koshi Tokunaga, Tomoki Kuroda, Junko Morikawa, Tokichi Minami
  • Publication number: 20230156326
    Abstract: A first image capturing unit (203 to 205) configured to capture an image using a lens placed on a first surface, a second image capturing unit (201 and 202) configured to capture an image using a lens placed on a second surface, the second image capturing unit being configured to switch to first image capturing using a first lens and second image capturing using a second lens with a wider angle than an angle of view of the first lens, and a control unit configured to perform control to, during the image capturing by the second image capturing unit, in response to a user operation for changing from a still image capturing mode to a moving image capturing mode, switch to the moving image capturing mode and also switch from the first image capturing using the first lens to the second image capturing using the second lens, are included.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Inventors: YOSHIHIRO FUNATSU, KOKI KITAYA, Junko MORIKAWA
  • Publication number: 20230156325
    Abstract: An electronic apparatus including a first lens and a second lens at a first side, the second lens having a angle of view different from that of the first lens, includes a switching unit configured to switch first imaging via the first lens and second imaging via the second lens, and a control unit configured to control display of items corresponding to a plurality of respective imaging modes, wherein the control unit is configured to, in a case where the second imaging is being performed, control display of a first item and a second item in different display modes, the first item corresponding to an imaging mode that enables the first imaging and the second imaging, the second item corresponding to an imaging mode that enables the first imaging and disables the second imaging.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Inventors: SEIJI OGAWA, Junko MORIKAWA, KEIKO YAMADA
  • Publication number: 20220116551
    Abstract: An image providing system capable of quickly providing a plurality of different cropped images is disclosed. The image providing system acquires position information about a position of a user designated by the user. The image providing system determines a range of an image that was captured by an image capturing unit, the range corresponding to the position information as a cropping range, before the image capturing unit starts a series of image capturing in which the image capturing unit captures a plurality of images. After the series of image capturing is started, the system applies cropping that cuts out a part of a captured image based on the cropping range. During the series of image capturing, the system provides a cropped image to which the cropping has been applied in a way in which a user can obtain the cropped image.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Tomonobu Hiraishi, Koshi Tokunaga, Tomoki Kuroda, Junko Morikawa, Tokichi Minami
  • Patent number: 7883878
    Abstract: Hydrochloric acid, sulfuric acid or an L-lysine solution having an equivalent ratio of anion/L-lysine higher than 0.95 is added to a raw material L-lysine solution having an equivalent ratio of anion/L-lysine lower than 0.68 to adjust the equivalent ratio of anion/L-lysine of the raw material solution to be in the range of 0.68 to 0.95, and the obtained L-lysine solution or a concentrate thereof is granulated and dried to obtain a dry granulated product having a high L-lysine content and showing low caking property and low hygroscopic property.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: February 8, 2011
    Assignee: Ajinomoto Co., Inc.
    Inventors: Takeshi Kushiki, Junko Morikawa, Kazuhiko Hasegawa
  • Publication number: 20090017507
    Abstract: Hydrochloric acid, sulfuric acid or an L-lysine solution having an equivalent ratio of anion/L-lysine higher than 0.95 is added to a raw material L-lysine solution having an equivalent ratio of anion/L-lysine lower than 0.68 to adjust the equivalent ratio of anion/L-lysine of the raw material solution to be in the range of 0.68 to 0.95, and the obtained L-lysine solution or a concentrate thereof is granulated and dried to obtain a dry granulated product having a high L-lysine content and showing low caking property and low hygroscopic property.
    Type: Application
    Filed: July 14, 2008
    Publication date: January 15, 2009
    Applicant: AJINOMOTO CO., INC.
    Inventors: Takeshi KUSHIKI, Junko MORIKAWA, Kazuhiko HASEGAWA
  • Patent number: 7416740
    Abstract: Hydrochloric acid, sulfuric acid or an L-lysine solution having an equivalent ratio of anion/L-lysine higher than 0.95 is added to a raw material L-lysine solution having an equivalent ratio of anion/L-lysine lower than 0.68 to adjust the equivalent ratio of anion/L-lysine of the raw material solution to be in the range of 0.68 to 0.95, and the obtained L-lysine solution or a concentrate thereof is granulated and dried to obtain a dry granulated product having a high L-lysine content and showing low caking property and low hygroscopic property.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: August 26, 2008
    Assignee: Ajinomoto Co., Inc.
    Inventors: Takeshi Kushiki, Junko Morikawa, Kazuhiko Hasegawa
  • Publication number: 20050002435
    Abstract: A temperature change is applied to at least a portion of a sample to be measured while measuring the thermal characteristic of a minute portion of the sample based on the temperature change by using infrared ray. There are provided a method and an apparatus which enable the thermal analysis of a minute portion of the sample.
    Type: Application
    Filed: November 19, 2002
    Publication date: January 6, 2005
    Inventors: Toshimasa Hashimoto, Junko Morikawa
  • Publication number: 20030152633
    Abstract: Hydrochloric acid, sulfuric acid or an L-lysine solution having an equivalent ratio of anion/L-lysine higher than 0.95 is added to a raw material L-lysine solution having an equivalent ratio of anion/L-lysine lower than 0.68 to adjust the equivalent ratio of anion/L-lysine of the raw material solution to be in the range of 0.68 to 0.95, and the obtained L-lysine solution or a concentrate thereof is granulated and dried to obtain a dry granulated product having a high L-lysine content and showing low caking property and low hygroscopic property.
    Type: Application
    Filed: January 24, 2003
    Publication date: August 14, 2003
    Applicant: AJINOMOTO CO., INC.
    Inventors: Takeshi Kushiki, Junko Morikawa, Kazuhiko Hasegawa
  • Patent number: 6417035
    Abstract: It is an object of the invention to solve a problem that a gate breakdown voltage and RF characteristics of a field effect transistor, which is provided with a double recess composed of a wide recess and a narrow recess, is not satisfactory. This problem results from the fact that a AlGaAs layer is exposed on a surface of the wide recess. The method for fabricating the field effect transistor comprise the steps of successively forming the first active layer, the first stopper layer, the second active layer, the second stopper layer and the third active layer on a substrate, forming a wide recess by etching a predetermined part of the third active layer till the second stopper is exposed, exposing the second active layer by removing the second stopper layer exposed on the bottom surface of the wide recess, and forming a narrow recess, which has a smaller aperture area than that of the wide recess, by etching a predetermined part of the exposed second active layer till the first stopper layer is exposed.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: July 9, 2002
    Assignee: NEC Corporation
    Inventor: Junko Morikawa
  • Patent number: 6399430
    Abstract: A field effect transistor has a preselected build up resistance with respect to an I-V characteristic of the transistor. In this event, a first GaAs layer is formed on a GaAs substrate. Further, an AlGaAs layer is formed on the first GaAs layer and has a predetermined impurity concentration and a preselected Al composition ratio. Moreover, a gate electrode is placed on the AlGaAs layer to form a schottky contact with the AlGaAs layer. In addition, a second GaAs layers are arranged on both sides of the gate electrode via a recess and are formed on said AlGaAs layer. Finally, source and drain electrodes are formed on the second GaAs layers. With such a structure, the Al composition ratio is determined within a preselected range defined by a relationship between the impurity concentration and the build up resistance.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: June 4, 2002
    Assignee: NEC Corporation
    Inventor: Junko Morikawa
  • Patent number: 6373081
    Abstract: A field effect transistor includes (a) a semi-insulating GaAs substrate, (b) a step-doped structured active layer including an n type GaAs layer deposited on the substrate, and an n− type GaAs layer or a non-doped GaAs layer deposited on the n type GaAs layer, the n− type GaAs layer or non-doped GaAs layer being formed with at least one recess, and (c) a gate electrode formed in the recess so that the gate electrode is oriented in such a direction that drain current runs in the active layer along crystal orientation [01(−1)]. The field effect transistor enhances linearity of transfer conductance, and further improves strain characteristic.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventors: Junko Morikawa, Hidemasa Takahashi, Kazunori Asano
  • Publication number: 20020016083
    Abstract: It is an object of the invention to solve a problem that a gate breakdown voltage and RF characteristics of a field effect transistor, which is provided with a double recess composed of a wide recess and a narrow recess, is not satisfactory. This problem results from the fact that aAlGaAs layer is exposed on a surface of the wide recess. The method for fabricating the field effect transistor comprise the steps of successively forming the first active layer, the first stopper layer, the second active layer, the second stopper layer and the third active layer on a substrate, forming a wide recess by etching a predetermined part of the third active layer till the second stopper is exposed, exposing the second active layer by removing the second stopper layer exposed on the bottom surface of the wide recess, and forming a narrow recess, which has a smaller aperture area than that of the wide recess, by etching a predetermined part of the exposed second active layer till the first stopper layer is exposed.
    Type: Application
    Filed: September 1, 1999
    Publication date: February 7, 2002
    Inventor: JUNKO MORIKAWA
  • Patent number: 6172384
    Abstract: It is an object of the invention to solve a problem that a gate breakdown voltage and RF characteristics of a field effect transistor, which is provided with a double recess composed of a wide recess and a narrow recess, is not satisfactory. This problem results from the fact that a AlGaAs layer is exposed on a surface of the wide recess. The method for fabricating the field effect transistor comprise the steps of successively forming the first active layer, the first stopper layer, the second active layer, the second stopper layer and the third active layer on a substrate, forming a wide recess by etching a predetermined part of the third active layer till the second stopper is exposed, exposing the second active layer by removing the second stopper layer exposed on the bottom surface of the wide recess, and forming a narrow recess, which has a smaller aperture area than that of the wide recess, by etching a predetermined part of the exposed second active layer till the first stopper layer is exposed.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: January 9, 2001
    Assignee: NEC Corporation
    Inventor: Junko Morikawa
  • Patent number: 6163041
    Abstract: A field effect transistor has a preselected build up resistance with respect to an I-V characteristic of the transistor. In this event, a first GaAs layer is formed on a GaAs substrate. Further, an AlGaAs layer is formed on the first GaAs layer and has a predetermined impurity concentration and a preselected Al composition ratio. Moreover, a gate electrode is placed on the AlGaAs layer to form a schottky contact with the AlGaAs layer. In addition, a second GaAs layers are arranged on both sides of the gate electrode via a recess and are formed on said AlGaAs layer. Finally, source and drain electrodes are formed on the second GaAs layers. With such a structure, the Al composition ratio is determined within a preselected range defined by a relationship between the impurity concentration and the build up resistance.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: December 19, 2000
    Assignee: NEC Corporation
    Inventor: Junko Morikawa
  • Patent number: 6033942
    Abstract: A comb-shape MESFET assembly has a plurality of unit FETs including first, second and third groups of unit FETs. The pinch-off voltages of the unit FETs are different from group to group by a step difference. The different pinch-off voltages provide a tailored change in the third-order intermodulation distortion in the output of the MESFET assembly. The step difference in the pinch-off voltage is generated by different thicknesses or impurity concentrations of a semiconductor active layer, different gate length of the unit FETs or different types of stress in the gate insulator films.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: March 7, 2000
    Assignee: NEC Corporation
    Inventors: Hidemasa Takahashi, Junko Morikawa
  • Patent number: 5834802
    Abstract: A comb-shape MESFET assembly has a plurality of unit FETs including first, second and third groups of unit FETs. The pinch-off voltages of the unit FETs are different from group to group by a step difference. The different pinch-off voltages provide a tailored change in the third-order intermodulation distortion in the output of the MESFET assembly. The step differences in the pinch-off voltage is generated by different thicknesses or impurity concentrations of a semiconductor active layer, different gate length of the unit FETs or different types of stress in the gate insulator films.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: November 10, 1998
    Assignee: NEC Corporation
    Inventors: Hidemasa Takahashi, Junko Morikawa