Patents by Inventor Junko Ogino

Junko Ogino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960225
    Abstract: An image forming apparatus includes, an image forming portion configured to form a toner image on a sheet using printing toner and apply powder adhesive on the sheet, a fixing portion configured to heat the toner image formed on the sheet and the powder adhesive applied on the sheet by the image forming portion and fix the toner image and the powder adhesive to the sheet, and a bonding portion configured to bond the sheet with the powder adhesive by reheating the sheet having been heated by the fixing portion. The bonding portion is arranged above the image forming portion.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: April 16, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koji Yamaguchi, Kohei Matsuda, Hiroki Ogino, Yasushi Katsuta, Kaori Noguchi, Junko Hirata, Akira Kuroda, Yuki Nishizawa, Tsutomu Shimano, Toru Oguma
  • Patent number: 7613960
    Abstract: There is provided a semiconductor test apparatus which uses a test processor to apply a test signal to a DUT having a semiconductor device within it to determine whether the memory is acceptable or not on the basis of a response signal, and uses a repair analysis computing unit to analyze the result of the test to determine how to replace a defective cell of the memory with a spare line. The repair analysis computing unit includes a fail memory which stores test results and a general-purpose repair analysis part which analyzes the test results in accordance with an MRA program and inserts and executes a user function of a user analysis program between units of analysis processing.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: November 3, 2009
    Assignee: Advantest Corporation
    Inventors: Kazuyoshi Okawa, Junko Ogino, Masayuki Yoshinaga, Hajime Honda
  • Publication number: 20070265794
    Abstract: There is provided a semiconductor test apparatus which uses a test processor to apply a test signal to a DUT having a semiconductor device within it to determine whether the memory is acceptable or not on the basis of a response signal, and uses a repair analysis computing unit to analyze the result of the test to determine how to replace a defective cell of the memory with a spare line. The repair analysis computing unit includes a fail memory which stores test results and a general-purpose repair analysis part which analyzes the test results in accordance with an MRA program and inserts and executes a user function of a user analysis program between units of analysis processing.
    Type: Application
    Filed: February 18, 2004
    Publication date: November 15, 2007
    Applicant: Advantest Corporation
    Inventors: Kazuyoshi Okawa, Junko Ogino, Masayuki Yoshinaga, Hajime Honda
  • Patent number: 5867435
    Abstract: In a repair method for a memory device, a process for determining whether or not repair is possible is first performed, following which processes are carried out for determining whether or not repair of failed lines is possible and whether or not repair of failed bits is possible. It is then determined whether or not a limit exists for a limbo portion, and if a limit exists, failure address connections of spare column portions are extracted from a buffer memory, and a rule check of the limbo portion and an adjustment of repair addresses is carried out in one-block portions for the obtained repair addresses.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: February 2, 1999
    Assignee: Advantest Corporation
    Inventor: Junko Ogino