Patents by Inventor Junlei TAO

Junlei TAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11276645
    Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 15, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Nan Zhao, Wenxu Xie, Junlei Tao, Shanghsuan Chiang, HuiLi Fu
  • Publication number: 20220020659
    Abstract: Embodiments of this application disclose a packaged chip and a method for manufacturing a packaged chip. The packaged chip includes a substrate, a chip, and a heat sink. The heat sink includes a first bracket, a second bracket, and a cover. The first bracket and the second bracket are disposed on the substrate. The cover is supported on the substrate by the first bracket and the second bracket. The first bracket is a sealed annular bracket. The first bracket and the cover encircle a first space. The chip is accommodated in the first space. A thermal interface material is disposed between the chip and the cover. A hole connected to the first space is provided on the cover. The hole and the first space are filled with a filling material. The second bracket is located outside the first space.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Inventors: Jiantao ZHENG, Nan ZHAO, Shanghsuan CHIANG, Xiao HU, Junlei TAO, Yu JIANG, Jianbiao LU
  • Publication number: 20200381361
    Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Nan ZHAO, Wenxu XIE, Junlei TAO, Shanghsuan CHIANG, HuiLi FU