Patents by Inventor Junli Gu
Junli Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9792228Abstract: A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a set of memory locations. The method then selects a cache replacement policy based on the value of the write count and selecting a block within the set for writing data using the selected cache replacement policy. The selected cache replacement policy can introduce a randomized selection.Type: GrantFiled: March 28, 2014Date of Patent: October 17, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Zhe Wang, Yuan Xie, Yi Xu, Junli Gu, Ting Cao
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Patent number: 9767043Abstract: A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.Type: GrantFiled: March 28, 2014Date of Patent: September 19, 2017Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Zhe Wang, Yuan Xie, Yi Xu, Junli Gu, Ting Cao
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Patent number: 9652390Abstract: Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. The method includes storing information indicating that the first cache requested the plurality of data items. The information may include an address for each of the plurality of data items. The method includes determining based at least on the stored information to move the plurality of data items to the second cache. The method includes moving the plurality of data items to the second cache. The method may include determining a time interval between receiving the indication that the first cache requested the plurality of data items and moving the plurality of data items to the second cache. A scratch pad memory is disclosed.Type: GrantFiled: August 5, 2014Date of Patent: May 16, 2017Assignee: Advanced Micro Devices, Inc.Inventors: JunLi Gu, Bradford M. Beckmann, Yuan Xie
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Patent number: 9639359Abstract: Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.Type: GrantFiled: May 21, 2013Date of Patent: May 2, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Yuan Xie, Junli Gu
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Patent number: 9552301Abstract: A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.Type: GrantFiled: July 15, 2013Date of Patent: January 24, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Zhe Wang, Junli Gu, Yi Xu
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Patent number: 9317448Abstract: A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.Type: GrantFiled: July 30, 2013Date of Patent: April 19, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Zhe Wang, Xie Yuan, Junli Gu, Yi Xu, ShuChang Shan, Shuai Mu, Ting Cao
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Publication number: 20160098275Abstract: Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.Type: ApplicationFiled: May 21, 2013Publication date: April 7, 2016Applicant: Advanced Micro Devices, Inc.Inventors: Yuan Xie, Junli Gu
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Publication number: 20160041909Abstract: Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. The method includes storing information indicating that the first cache requested the plurality of data items. The information may include an address for each of the plurality of data items. The method includes determining based at least on the stored information to move the plurality of data items to the second cache. The method includes moving the plurality of data items to the second cache. The method may include determining a time interval between receiving the indication that the first cache requested the plurality of data items and moving the plurality of data items to the second cache. A scratch pad memory is disclosed.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Applicant: ADVANCED MICRO DEVICES, INC.Inventors: JunLi Gu, Bradford M. Beckmann, Yuan Xie
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Publication number: 20150100735Abstract: A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.Type: ApplicationFiled: March 28, 2014Publication date: April 9, 2015Applicant: Advanced Micro Devices, IncInventors: Zhe WANG, Yuan XIE, Yi XU, Junli GU, Ting CAO
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Publication number: 20150100739Abstract: A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a set of memory locations. The method then selects a cache replacement policy based on the value of the write count and selecting a block within the set for writing data using the selected cache replacement policy. The selected cache replacement policy can introduce a randomized selection.Type: ApplicationFiled: March 28, 2014Publication date: April 9, 2015Applicant: Advanced Micro Devices, Inc.Inventors: Zhe WANG, Yuan Xie, Yi Xu, Junli Gu, Ting Cao
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Publication number: 20150039836Abstract: A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.Type: ApplicationFiled: July 30, 2013Publication date: February 5, 2015Applicant: Advanced Micro Devices, Inc.Inventors: Zhe Wang, Xie Yuan, Junli Gu, Yi Xu, ShuChang Shan, Shuai Mu, Ting Cao
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Publication number: 20150019823Abstract: A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.Type: ApplicationFiled: July 15, 2013Publication date: January 15, 2015Inventors: Zhe Wang, Junli Gu, Yi Xu