Patents by Inventor Junli Gu

Junli Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9792228
    Abstract: A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a set of memory locations. The method then selects a cache replacement policy based on the value of the write count and selecting a block within the set for writing data using the selected cache replacement policy. The selected cache replacement policy can introduce a randomized selection.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 17, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhe Wang, Yuan Xie, Yi Xu, Junli Gu, Ting Cao
  • Patent number: 9767043
    Abstract: A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: September 19, 2017
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Zhe Wang, Yuan Xie, Yi Xu, Junli Gu, Ting Cao
  • Patent number: 9652390
    Abstract: Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. The method includes storing information indicating that the first cache requested the plurality of data items. The information may include an address for each of the plurality of data items. The method includes determining based at least on the stored information to move the plurality of data items to the second cache. The method includes moving the plurality of data items to the second cache. The method may include determining a time interval between receiving the indication that the first cache requested the plurality of data items and moving the plurality of data items to the second cache. A scratch pad memory is disclosed.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 16, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: JunLi Gu, Bradford M. Beckmann, Yuan Xie
  • Patent number: 9639359
    Abstract: Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: May 2, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yuan Xie, Junli Gu
  • Patent number: 9552301
    Abstract: A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: January 24, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhe Wang, Junli Gu, Yi Xu
  • Patent number: 9317448
    Abstract: A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: April 19, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Zhe Wang, Xie Yuan, Junli Gu, Yi Xu, ShuChang Shan, Shuai Mu, Ting Cao
  • Publication number: 20160098275
    Abstract: Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.
    Type: Application
    Filed: May 21, 2013
    Publication date: April 7, 2016
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Yuan Xie, Junli Gu
  • Publication number: 20160041909
    Abstract: Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. The method includes storing information indicating that the first cache requested the plurality of data items. The information may include an address for each of the plurality of data items. The method includes determining based at least on the stored information to move the plurality of data items to the second cache. The method includes moving the plurality of data items to the second cache. The method may include determining a time interval between receiving the indication that the first cache requested the plurality of data items and moving the plurality of data items to the second cache. A scratch pad memory is disclosed.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 11, 2016
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: JunLi Gu, Bradford M. Beckmann, Yuan Xie
  • Publication number: 20150100735
    Abstract: A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.
    Type: Application
    Filed: March 28, 2014
    Publication date: April 9, 2015
    Applicant: Advanced Micro Devices, Inc
    Inventors: Zhe WANG, Yuan XIE, Yi XU, Junli GU, Ting CAO
  • Publication number: 20150100739
    Abstract: A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a set of memory locations. The method then selects a cache replacement policy based on the value of the write count and selecting a block within the set for writing data using the selected cache replacement policy. The selected cache replacement policy can introduce a randomized selection.
    Type: Application
    Filed: March 28, 2014
    Publication date: April 9, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Zhe WANG, Yuan Xie, Yi Xu, Junli Gu, Ting Cao
  • Publication number: 20150039836
    Abstract: A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Zhe Wang, Xie Yuan, Junli Gu, Yi Xu, ShuChang Shan, Shuai Mu, Ting Cao
  • Publication number: 20150019823
    Abstract: A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Inventors: Zhe Wang, Junli Gu, Yi Xu