Patents by Inventor Junnan Zhao

Junnan Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190355675
    Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: Kyu-Oh LEE, Sai VADLAMANI, Rahul JAIN, Junnan ZHAO, Ji Yong PARK, Cheng XU, Seo Young KIM
  • Publication number: 20190304933
    Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Cheng XU, Kyu-Oh LEE, Junnan ZHAO, Rahul JAIN, Ji Yong PARK, Sai VADLAMANI, Seo Young KIM
  • Publication number: 20190304661
    Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
  • Publication number: 20190295937
    Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a trace disposed on a conductive layer. The semiconductor package has one or more adhesion anchoring points and a plurality of portions on the trace. An adhesion anchoring point is between two portions on the trace. A surface roughness of an adhesion anchoring point is greater than a surface roughness of a portion on the trace. The trace may be a high-speed input/output (HSIO) trace. The semiconductor package may include via pads disposed on each end of the trace, and a dielectric disposed on the trace. The dielectric is patterned to form openings on the dielectric that expose second portions on the trace. The dielectric remains over the portions. The semiconductor package may have a chemical treatment disposed on the exposed openings on the trace to form the adhesion anchoring points.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 26, 2019
    Inventors: Chong ZHANG, Ying WANG, Cheng XU, Hongxia FENG, Meizi JIAO, Junnan ZHAO, Yikang DENG
  • Publication number: 20190287815
    Abstract: The systems and methods described herein provide for the fabrication of semiconductor package substrates having magnetic inductors formed in at least a portion of the through-holes formed in the semiconductor package substrate. Such magnetic inductors are formed without exposing the magnetic material disposed in the through-hole to any wet chemistry (desmear, electro-less plating, etc.) processes by sealing the magnetic material with a patterned sealant (e.g., patterned dry film resist) which seals the magnetic material prior to performing steps involving wet chemistry on the semiconductor package substrate. Such beneficially minimizes or even eliminates the contamination of wet chemistry reagents by the magnetic material should the magnetic material remain exposed during the wet chemistry processes. The patterned sealant is removed subsequent to the semiconductor package processing steps involving wet chemistry.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventors: CHENG XU, CHONG ZHANG, YIKANG DENG, JUNNAN ZHAO, YING WANG
  • Publication number: 20190287934
    Abstract: Techniques for fabricating a cored or coreless semiconductor package having one or more magnetic bilayer structures embedded therein are described. A magnetic bilayer structure includes a magnetic layer and a dielectric layer. For one technique, fabricating a cored or coreless semiconductor package includes: depositing a seed layer on a build-up layer; forming a raised pad structure and a trace on the seed layer; removing one or more uncovered portions of the seed layer to uncover top surfaces of one or more portions of the build-up layer; applying a magnetic bilayer structure on the raised pad structure, the trace, any unremoved portion of the seed layer, and the top surfaces of the one or more portions of the build-up layer, the magnetic bilayer structure comprises a magnetic layer and a dielectric layer; and forming a conductive structure on the raised pad structure. Other techniques are also described.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Inventors: Yikang DENG, Jonathan ROSCH, Andrew BROWN, Junnan ZHAO
  • Publication number: 20190279806
    Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 12, 2019
    Inventors: Kristof DARMAWIKARTA, Srinivas PIETAMBARAM, Sandeep GAAN, Sri Ranga Sai BOYAPATI, Prithwish CHATTERJEE, Sameer PAITAL, Rahul JAIN, Junnan ZHAO
  • Publication number: 20190272936
    Abstract: Embodiments include inductors with embedded magnetic cores and methods of forming such inductors. Some embodiments may include an integrated circuit package that utilizes such inductors. For example, the integrated circuit package may include an integrated circuit die and a multi-phase voltage regulator electrically coupled to the integrated circuit die. In an embodiment, the multi-phase voltage regulator includes a substrate core and a plurality of inductors in the substrate core. In an embodiment, the inductors may include a conductive loop in and around the substrate core. In an embodiment, the conductive loops are electrically coupled to a voltage out line. Embodiments may also include a magnetic core surrounded by the conductive loops.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 5, 2019
    Inventors: Chong ZHANG, Cheng XU, Ying WANG, Junnan ZHAO, Meizi JIAO, Yikang DENG
  • Publication number: 20190274217
    Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Inventors: Chong ZHANG, Ying WANG, Junnan ZHAO, Cheng XU, Yikang DENG
  • Patent number: 10373951
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Publication number: 20190206780
    Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: Intel Corporation
    Inventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li