Abstract: The antenna device includes a first antenna 11 that includes a first ground terminal 12; a second antenna 18 that includes a second ground terminal 20; a ground conductor 28 to which the first antenna 11 is connected through the first ground terminal 12 and the second antenna 18 is connected through the second ground terminal 20; and a phase shifter 24 that controls a phase difference between a first current ie1 and a second current ie2. The phase shifter 24 controls the phase difference between the first current ie1 and the second current ie2 so that the first current ie1 and the second current ie2 have components to cancel each other.

Abstract: The antenna device includes a first antenna 11 that includes a first ground terminal 12; a second antenna 18 that includes a second ground terminal 20; a ground conductor 28 to which the first antenna 11 is connected through the first ground terminal 12 and the second antenna 18 is connected through the second ground terminal 20; and a phase shifter 24 that controls a phase difference between a first current ie1 and a second current ie2. The phase shifter 24 controls the phase difference between the first current ie1 and the second current ie2 so that the first current ie1 and the second current ie2 have components to cancel each other.

Abstract: The antenna device includes a first antenna 11 that includes a first ground terminal 12; a second antenna 18 that includes a second ground terminal 20; a ground conductor 28 to which the first antenna 11 is connected through the first ground terminal 12 and the second antenna 18 is connected through the second ground terminal 20; and a phase shifter 24 that controls a phase difference between a first current ie1 and a second current ie2. The phase shifter 24 controls the phase difference between the first current ie1 and the second current ie2 so that the first current ie1 and the second current ie2 have components to cancel each other.

Abstract: An antenna apparatus that can be miniaturized without causing inference caused by antenna currents to be occurred if the high band of a dual band wireless system is close to the band of another wireless system in a wireless communication apparatus incorporating the dual band wireless system and another wireless system is provided. A first switch 5 blocks passage of a signal of a high band (first frequency) and allows passage of a signal of a low band (second frequency). A second switch 6 blocks passage of a signal of the low band (second frequency) and allows passage of a signal of the high band (first frequency). Accordingly, the antenna apparatus operates as a dipole antenna with no antenna current flowing into a feeder line at the first frequency and operates as a monopole antenna wherein a radiation element and a feeder line making up the dipole antenna becomes a radiation element at the second frequency lower than the first frequency.

Abstract: An antenna apparatus that can be miniaturized without causing inference caused by antenna currents to be occurred if the high band of a dual band wireless system is close to the band of another wireless system in a wireless communication apparatus incorporating the dual band wireless system and another wireless system is provided. A first switch 5 blocks passage of a signal of a high band (first frequency) and allows passage of a signal of a low band (second frequency). A second switch 6 blocks passage of a signal of the low band (second frequency) and allows passage of a signal of the high band (first frequency). Accordingly, the antenna apparatus operates as a dipole antenna with no antenna current flowing into a feeder line at the first frequency and operates as a monopole antenna wherein a radiation element and a feeder line making up the dipole antenna becomes a radiation element at the second frequency lower than the first frequency.

Abstract: In a synchronous detection circuit, an interpolation circuit regulates an interpolation calculation coefficient based on phase shift information when carrying out interpolation calculation processing over a digitally converted received signal. A sampling circuit samples interpolation data using a recovered clock as a reference and two clocks having phases which are advanced and delayed with respect to the recovered clock. A phase shift detecting circuit monitors a phase shift using three sampling data output from the sampling circuit and outputting phase shift information to the interpolation circuit when detecting a predetermined phase shift. A demodulating circuit performs demodulation processing using the data subjected to the sampling with the recovered clock output from the sampling circuit. Where a synchronous shift is detected, the interpolation circuit performs regulation to match a timing having a maximum signal-to-noise ratio and the recovered clock based on the amount of the phase shift.

Abstract: A synchronous detection circuit includes: an interpolation circuit for regulating an interpolation calculation coefficient based on phase shift information when carrying out an interpolation calculation processing over a received signal which is digitally converted; a secondary sampling circuit for sampling interpolation data output from the interpolation circuit by using a recovered clock to be a reference and two clocks having phases corresponding to one processing clock which are advanced and delayed for the recovered clock; a phase shift detecting circuit for monitoring a shift of a phase by using three sampling data output from the secondary sampling circuit and outputting phase shift information to the interpolation circuit when detecting a predetermined phase shift; and a demodulating circuit for carrying out a demodulation processing by using the data subjected to the sampling with the recovered clock output from the secondary sampling circuit.