Abstract: A semiconductor storage device with high integration is capable of performing high speed access. The semiconductor storage device is constituted in such a way that it causes one contact to be connected with a primary bit-line, further it causes four sub bit-lines to be connected through four bank selection transistor, furthermore, it causes one contact to be connected to a virtual GND line, moreover, it causes two sub bit-lines to be connected through two bank selection transistors. The respective sub bit-lines are arranged in parallel to signal inputted to six bank selection lines, and in parallel to primary bit-line. Two virtual GND lines which are arranged at right and left of the primary bit-line. The memory cell transistor is capable of being selected according to combination of level of the two virtual GND lines. This causes bank selection lines to be reduced, further it causes cell array to be shortened in bit direction, furthermore, it causes cell array area to be reduced.

Abstract: A semiconductor memory having burst mode operation includes a memory cell array, a sense amplifier circuit determining data of memory cells, a latch circuit having first and second latch groups and latching data of a sense amplifier, an enable circuit provided with an chip enable signal and controlling readout operation the semiconductor. The enable circuit instructs the circuit for readout operation to activate until the latch circuit latches data even if the chip enable signal indicates stopping the readout operation of semiconductor memory to output data of memory cells correctly.

Abstract: A semiconductor storage device with high integration is capable of performing high speed access. The semiconductor storage device is constituted in such a way that it causes one contact to be connected with a primary bit-line, further it causes four sub bit-lines to be connected through four bank selection transistor, furthermore, it causes one contact to be connected to a virtual GND line, moreover, it causes two sub bit-lines to be connected through two bank selection transistors. The respective sub bit-lines are arranged in parallel to signal inputted to six bank selection lines, and in parallel to primary bit-line. Two virtual GND lines which are arranged at right and left of the primary bit-line. The memory cell transistor is capable of being selected according to combination of level of the two virtual GND lines. This causes bank selection lines to be reduced, further it causes cell array to be shortened in bit direction, furthermore, it causes cell array area to be reduced.

Abstract: A semiconductor storage device with high integration is capable of performing high speed access. The semiconductor storage device is constituted in such a way that it causes one contact to be connected with a primary bit-line, further it causes four sub bit-lines to be connected through four bank selection transistor, furthermore, it causes one contact to be connected to a virtual GND line, moreover, it causes two sub bit-lines to be connected through two bank selection transistors. The respective sub bit-lines are arranged in parallel to signal inputted to six bank selection lines, and in parallel to primary bit-line. Two virtual GND lines which are arranged at right and left of the primary bit-line. The memory cell transistor is capable of being selected according to combination of level of the two virtual GND lines. This causes bank selection lines to be reduced, further it causes cell array to be shortened in bit direction, furthermore, it causes cell array area to be reduced.

Abstract: A semiconductor memory having burst mode operation includes a memory cell array, a sense amplifier circuit determining data of memory cells, a latch circuit having first and second latch groups and latching data of a sense amplifier, an enable circuit provided with an chip enable signal and controlling readout operation the semiconductor. The enable circuit instructs the circuit for readout operation to activate until the latch circuit latches data even if the chip enable signal indicates stopping the readout operation of semiconductor memory to output data of memory cells correctly.

Abstract: A semiconductor storage device may shorten burn-in test times without adversely affecting a normal mode of operation. According to one embodiment, a determination circuit 60 can select multiple memory section (10 and 20) simultaneously in a burn-in test, and prevent such a simultaneous selection of multiple memory sections (10 and 20) in a normal mode of operation.