Abstract: An apparatus and methods for timing mismatch in a power amplifier includes a segmented PA with two-path timing mismatch calibration to improve ACLR performance over different signal transitions, process, voltage and temperature (PVT) variations and device aging; a fast and efficient algorithm for measuring and calibrating the delay of two paths (signal path and control path); a signal magnitude variation detection circuit, such as flash ADC, with improved comparator's performance for RF signal processing and minimum delay. A method for choosing the threshold voltage of the magnitude variation detection circuit, according to status of the signals and orthogonal frequency-division multiplexing (OFDM) related standards; other critical blocks.