Abstract: The present invention relates to a signal duty cycle adaptive-adjustment circuit and method for a receiving terminal. In one embodiment, the circuit includes an analog level comparison circuit, a preprocessing circuit, a first path switch, a second path switch, a decoding circuit, a parameter extraction and estimation circuit, an error generation circuit, a filter feedback circuit and a digital-to-analog conversion circuit. The analog level comparison circuit receives a valid signal according to a reference level to generate a duty cycle signal. The preprocessing circuit preprocesses the duty cycle signal. When the first path switch is turned on, the parameter extraction and estimation circuit acquires duty cycle information from the duty cycle signal to generate a duty cycle deviation. The error generation circuit processes the duty cycle deviation to generate an error signal.

Abstract: The present invention relates to a signal duty cycle adaptive-adjustment circuit and method for a receiving terminal. In one embodiment, the circuit includes an analog level comparison circuit, a preprocessing circuit, a first path switch, a second path switch, a decoding circuit, a parameter extraction and estimation circuit, an error generation circuit, a filter feedback circuit and a digital-to-analog conversion circuit. The analog level comparison circuit receives a valid signal according to a reference level to generate a duty cycle signal. The preprocessing circuit preprocesses the duty cycle signal. When the first path switch is turned on, the parameter extraction and estimation circuit acquires duty cycle information from the duty cycle signal to generate a duty cycle deviation. The error generation circuit processes the duty cycle deviation to generate an error signal.

Abstract: A chassis includes a main body having a backplane, a top cover plate, a bottom cover plate and left and right side plates connected with each other. An upper slide rail and a lower slide rail for securing single boards are provided in the main body, a fan is arranged at the upper position of the main body and a power distribution unit is arranged at the lower position of the main body, and a coupling element for coupling the fan with the power distribution unit is provided in the chassis. The coupling element may be a groove extending from the upper position to the lower position for accommodating cables and formed in the inner side of the side plate of the chassis, or may be two openings for passage of cables respectively provided at an upper position and a lower position of the side plate of the chassis.

Abstract: A chassis includes a main box body. The said main box body includes a back panel, an upper cover panel, a lower cover panel, a left side panel and a right side panel connected with each other. An upper single panel slideway and a lower single panel slideway are provided in the main box body for fixing single panels. A fan is provided on the top of the main box body. A power distribution unit is provided on the bottom of the main box body. A connection portion is provided in the chassis for connecting the fan and the power distribution unit. The connection portion is a groove provided from the top to the bottom of the side panel for holding acable or two holes provided on the upper and the lower locations of the side panel for guiding the cable.

Abstract: A method, system, and apparatus for synchronizing an asynchronous data transmission between a transmitter and a receiver are presented. For example, an elastic buffer can include a symbol storage coupled to receive transition data from a transmitter and to store the transition data in a plurality of addressable symbol storage elements; a write clock domain, which operates at a recovery clock, for selecting a symbol storage element of symbol storage to store the transition data, determining whether a SKIP ordered set has occurred, and deleting a SKIP symbol of the SKIP ordered set based on the determination to prevent the deleted SKIP symbol from being stored in symbol storage; and a read clock domain, which operates at a local clock, for selecting a symbol storage element of the symbol storage to retrieve the transition data as receiver data, determining whether a SKIP ordered set is occurring, adding a SKIP symbol to the receiver data based on the determination; and providing the receiver data to a receiver.