Abstract: A failure location specifying device that can specify a failure location even if the spatial resolution is insufficient includes: an EOFM measurement unit that calculates a phase difference between a measurement signal on the basis of reflected light in accordance with the operation of a circuit element arranged in a semiconductor device and a reference signal, and generates a phase map of the circuit element in the semiconductor device. A circuit simulation unit calculates the operation waveform of a circuit element included in the field of view that is extracted by a circuit extraction unit by a simulation. A phase calculation unit calculates a phase on the basis of the operation waveform calculated by the circuit simulation unit; and a phase map generation unit generates a phase map of the circuit element on the basis of the phase calculated by the phase calculation unit.

Abstract: This present invention is to obtain the appropriate number of fails by optimizing test conditions for a delay failure diagnosis. In a failure diagnosis system of an embodiment, a control unit controls a test device to test an integrated circuit a plurality of times while changing the test conditions to collect a fail log. A creation unit creates a test result map on the basis of the fail log. An extraction unit performs route tracking from a fail flip-flop in the fail log to obtain a primary failure candidate. An analysis unit computes by a simulation the delay and timing margin of the fail flip-flop in the fail log. A computing unit computes a matching degree between the timing margin of the simulation result and the test result map for each primary failure candidate. An output unit outputs a candidate having a high matching degree as a failure candidate.

Abstract: A circuit design supporting apparatus includes: an observation portion specifying section configured to specify a first portion with a high improvement effect of analysis easiness in failure analysis of an integrated circuit as an observation portion; and an element substitution performing section configured to substitute an element arranged in the observation portion by an analysis target element to which a failure analysis apparatus can appropriately conduct the failure analysis based on a data of the observation portion.

Abstract: A circuit design device decides placement of elements and interconnections included in a circuit, on the basis of connection information of the circuit. The circuit design device includes an equivalent fault class extracting unit, a weighting unit, and a placement deciding unit. The equivalent fault class extracting unit extracts one or more classes (hereinbelow referred to as “equivalent fault classes”) having, as members, interconnections (hereinbelow referred to as “equivalent fault interconnections”) which mutually cause an equivalent fault in the circuit. The weighting unit gives a greater weight to the equivalent fault class or the equivalent fault interconnections included in the equivalent fault class, as the number of the members in the equivalent fault class (hereinbelow referred to as the “number of equivalent fault interconnections”) increases.

Abstract: A circuit design supporting apparatus includes: an observation portion specifying section configured to specify a first portion with a high improvement effect of analysis easiness in failure analysis of an integrated circuit as an observation portion; and an element substitution performing section configured to substitute an element arranged in the observation portion by an analysis target element to which a failure analysis apparatus can appropriately conduct the failure analysis based on a data of the observation portion.

Abstract: A circuit design device decides placement of elements and interconnections included in a circuit, on the basis of connection information of the circuit. The circuit design device includes an equivalent fault class extracting unit, a weighting unit, and a placement deciding unit. The equivalent fault class extracting unit extracts one or more classes (hereinbelow referred to as “equivalent fault classes”) having, as members, interconnections (hereinbelow referred to as “equivalent fault interconnections”) which mutually cause an equivalent fault in the circuit. The weighting unit gives a greater weight to the equivalent fault class or the equivalent fault interconnections included in the equivalent fault class, as the number of the members in the equivalent fault class (hereinbelow referred to as the “number of equivalent fault interconnections”) increases.

Abstract: A circuit design program product to cause a computer to execute a circuit design process based on a test point insertion, includes: a step for making reference to a netlist to extract a plurality of equivalent faults fj; a step for searching a number n(fj) of test point required for a number of the equivalent fault keeping equivalent relation with a search object equivalent fault fj with each of a plurality of equivalent faults as the search object equivalent fault to become a predetermined number and a insertion position G(fj); a step for calculating probability p(fj) of a single stuck-at fault being included in a set of equivalent faults including at least a search object equivalent fault fj at an occasion when the relevant stuck-at fault takes place in the circuit; a step for calculating a parameter e(fj) derived by an equation: e(fj)=p(fj)/n(fj) on each pattern of an insertion position G(fj); and a step for determining the insertion position G(fmax) giving the maximum value among the calculated parameters

Abstract: A circuit design system has: a storage unit in which a netlist is stored; a fault-candidate extracting module configured to extract equivalent fault class Gi from the netlist; a judgment module configured to select a target node out of a plurality of nodes Ni1 to Niji included in the equivalent fault class Gi, wherein Ji is a number of nodes included in the equivalent fault class Gi; and an observation-point inserting module configured to update the netlist by inserting at least one observation point into the target node. The judgment module decides the target node based on the number Ji.

Abstract: A circuit design program product to cause a computer to execute a circuit design process based on a test point insertion, includes: a step for making reference to a netlist to extract a plurality of equivalent faults fj; a step for searching a number n(fj) of test point required for a number of the equivalent fault keeping equivalent relation with a search object equivalent fault fj with each of a plurality of equivalent faults as the search object equivalent fault to become a predetermined number and a insertion position G(fj); a step for calculating probability p(fj) of a single stuck-at fault being included in a set of equivalent faults including at least a search object equivalent fault fj at an occasion when the relevant stuck-at fault takes place in the circuit; a step for calculating a parameter e(fj) derived by an equation: e(fj)=p(fj)/n(fj) on each pattern of an insertion position G(fj); and a step for determining the insertion position G(fmax) giving the maximum value among the calculated parameters

Abstract: A circuit design system has: a storage unit in which a netlist is stored; a fault-candidate extracting module configured to extract equivalent fault class Gi from the netlist; a judgment module configured to select a target node out of a plurality of nodes Ni1 to Niji included in the equivalent fault class Gi, wherein Ji is a number of nodes included in the equivalent fault class Gi; and an observation-point inserting module configured to update the netlist by inserting at least one observation point into the target node. The judgment module decides the target node based on the number Ji.