Abstract: Embodiments of this application disclose a computing system, an addressing method, a compute node, and a program product, and pertain to the computing field. Each compute node in a computing system has a different first-level identifier, and a plurality of function modules in each compute node have different second-level identifiers. The second-level identifier is used for routing and addressing between function modules in a same compute node, and the first-level identifier and the second-level identifier are used for routing and addressing between function modules in different compute nodes. In other words, unified addressing is performed on the different compute nodes, and is also performed on the function modules in the same compute node. In this way, interconnection specifications used during communication between the compute nodes and communication in the compute node are consistent, complex protocol conversion is not needed, data processing efficiency is improved, and latency is reduced.

Abstract: When a memory controller reads target data in a memory, the memory controller reads the target data and first check code of the target data from the memory. The memory controller checks the target data using the first check code. If the check fails, it indicates that error data exists in the target data. The memory controller then performs error correction on the target data using the first check code. After failing to perform error correction on the target data using the first check code in the memory, the memory controller performs error correction on the target data using the second check code in the secondary storage.

Abstract: A memory access method comprises adding routing information to a memory page table, so that a memory management unit (MMU) queries, in a process of performing address translation on a virtual address (VA), the memory page table to obtain the routing information. After querying the memory page table and obtaining a physical address (PA), the MMU may directly route the PA based on the routing information, whereby a system address decoder (SAD) is not needed for further decoding the PA.

Abstract: A plurality of physical cores of a processor share a memory management unit (MMU) pool comprising a plurality of MMUs. The plurality of MMUs provides each physical core with an address translation function from a virtual address (VA) to a physical address (PA). If an address translation requirement of a physical core is high, for example, when a main memory is concurrently accessed, the plurality of MMUs can serve the physical core.

Abstract: This application discloses a method for compensating for a clock frequency deviation between two ends of a link, and a communication port. The method may be applied to a first port. The first port detects a quantity of protocol-aware signal extenders in a link between the first port and a second port, and generates a padding packet based on the quantity of protocol-aware signal extenders in the link. Then, the first port inserts the padding packet into a data stream to be sent to the second port.

Abstract: A link negotiation system includes a second device that determines a link configuration policy based on a status of a receiver of an interface of the second device, where the link configuration policy indicates an association relationship between a unidirectional logical lane and a unidirectional physical lane in a high-speed serial link between a first device and the second device, the unidirectional logical lane is a logical lane from the first device to the second device in the high-speed serial link, and the unidirectional physical lane is a physical lane from the first device to the second device in the high-speed serial link; and sends the link configuration policy to the first device.

Abstract: A memory access method comprises adding routing information to a memory page table, so that a memory management unit (MMU) queries, in a process of performing address translation on a virtual address (VA), the memory page table to obtain the routing information. After querying the memory page table and obtaining a physical address (PA), the MMU may directly route the PA based on the routing information, whereby a system address decoder (SAD) is not needed for further decoding the PA.

Abstract: A plurality of physical cores of a processor share a memory management unit (MMU) pool comprising a plurality of MMUs. The plurality of MMUs provides each physical core with an address translation function from a virtual address (VA) to a physical address (PA). If an address translation requirement of a physical core is high, for example, when a main memory is concurrently accessed, the plurality of MMUs can serve the physical core.

Abstract: When a memory controller may need to read target data in a memory, the memory controller reads the target data and first check code of the target data from the memory. The memory controller may check the target data using the first check code. If the check fails, it indicates that error data exists in the target data. The memory controller may perform error correction on the target data using the first check code. After failing to perform error correction on the target data using the first check code in the memory, the memory controller performs error correction on the target data using the second check code in the secondary storage, to ensure that the error correction is implemented on the target data.

Abstract: Embodiments of this application disclose a computing system, an addressing method, a compute node, and a program product, and pertain to the computing field. Each compute node in a computing system has a different first-level identifier, and a plurality of function modules in each compute node have different second-level identifiers. The second-level identifier is used for routing and addressing between function modules in a same compute node, and the first-level identifier and the second-level identifier are used for routing and addressing between function modules in different compute nodes. In other words, unified addressing is performed on the different compute nodes, and is also performed on the function modules in the same compute node. In this way, interconnection specifications used during communication between the compute nodes and communication in the compute node are consistent, complex protocol conversion is not needed, data processing efficiency is improved, and latency is reduced.

Abstract: A transmitter equalization parameter evaluation method and an apparatus are provided. The method provided in this application is used for evaluating a transmitter equalization parameter of a high-speed interface in a first device, and the method is performed by a second device connected to the first device over a communication link. The second device first detects a status of the communication link between the first device and the second device, where the communication link is constructed through the high-speed interface in the first device. When determining that the communication link is idle, the second device performs a transmitter equalization parameter evaluation process of the high-speed interface in the first device based on the communication link. When the communication link is idle, the transmitter equalization parameter evaluation process of the high-speed interface in the first device is started. This ensures efficiency of transmitter equalization parameter evaluation.

Abstract: A link negotiation system includes a second device that determines a link configuration policy based on a status of a receiver of an interface of the second device, where the link configuration policy indicates an association relationship between a unidirectional logical lane and a unidirectional physical lane in a high-speed serial link between a first device and the second device, the unidirectional logical lane is a logical lane from the first device to the second device in the high-speed serial link, and the unidirectional physical lane is a physical lane from the first device to the second device in the high-speed serial link; and sends the link configuration policy to the first device.

Abstract: A fingerprint chip package and method for processing same, relating to a field of biometric identification. The fingerprint chip package includes: a lead frame (1), a chip (2), and a plastic packaging part enclosing the lead frame (1) and the chip (2); the lead frame (1) comprises a base island (13), a connecting rib (11), and a golden finger (12); the base island (13) is used for bearing the chip (2); the connecting rib (11) is used for supporting the lead frame (1) and connecting the base island (13) via the golden finger (12); and the golden finger (12) is used for fixing the base island (13) and electrically connecting with the chip (2).

Abstract: A chip packaging structure comprises a die, a carrier, a die attach film, and a plastic package body. The die attach film is disposed on the bottom surface of the die, with a thickness of the die attach film being greater than or equal to 40 micrometers. The die is disposed on the carrier via the die attach film; and the plastic package body is disposed on the carrier and coats a top surface and side surfaces of the die, whereby the overall impact resistance of a chip is improved without changing the structure of the carrier, the expense for making a mold is saved, and moreover, the packaging structure is simple and easy for mass production.

Abstract: A chip packaging structure comprises a die, a carrier, a die attach film, and a plastic package body. The die attach film is disposed on the bottom surface of the die, with a thickness of the die attach film being greater than or equal to 40 micrometers. The die is disposed on the carrier via the die attach film; and the plastic package body is disposed on the carrier and coats a top surface and side surfaces of the die, whereby the overall impact resistance of a chip is improved without changing the structure of the carrier, the expense for making a mold is saved, and moreover, the packaging structure is simple and easy for mass production.

Abstract: A fingerprint chip package and method for processing same, relating to a field of biometric identification. The fingerprint chip package includes: a lead frame (1), a chip (2), and a plastic packaging part enclosing the lead frame (1) and the chip (2); the lead frame (1) comprises a base island (13), a connecting rib (11), and a golden finger (12); the base island (13) is used for bearing the chip (2); the connecting rib (11) is used for supporting the lead frame (1) and connecting the base island (13) via the golden finger (12); and the golden finger (12) is used for fixing the base island (13) and electrically connecting with the chip (2).