Abstract: A video encoder is disclosed. The video encoder comprises an integer level motion estimation hardware component configured to determine candidate integer level motion vectors for a video being encoded. The video encoder comprises a fractional motion estimation hardware component configured to receive the candidate integer level motion vectors from the integer level motion estimation hardware component and refine the candidate integer level motion vectors into candidate sub-pixel level motion vectors. The fractional motion estimation hardware component includes parallel pipelines configured to process coding units of a frame of the video in parallel across the parallel pipelines.

Abstract: A system comprises a source block buffer and a plurality of hardware motion estimation search processing units in communication with the source block buffer. The source block buffer is configured to store at least a portion of a source block of a source frame of a video. The plurality of hardware motion estimation search processing units are configured to perform at least a portion of a motion estimation for the source block at least in part in parallel across a plurality of different reference frames of the video.

Abstract: A disclosed system may include a hardware distortion data pipeline that may include (1) a quantization module that generates a quantized data set, (2) an inverse quantization module that generates, from the quantized data set, an inverse quantized data set by executing an inverse quantization of the quantized data set, and (3) an inverse transformation module that generates an inversely transformed data set by executing an inverse transformation of the inverse quantized data set. The system may also include a hardware determination pipeline that determines a distortion metric based on the inversely transformed data set and the residual frame data set, and a hardware token rate pipeline that determines, based on the quantized data set, a token rate for an encoding of the residual frame data set via a video encoding pipeline. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A disclosed computer-implemented method may include (1) selecting, from a video stream, a reference frame and a current frame, (2) collecting a reference histogram of the reference frame and a current histogram of the current frame, and (3) generating a smoothed reference histogram by applying a smoothing function to at least a portion of the reference histogram. In some examples, the computer-implemented method may also include (1) determining a similarity metric between the smoothed reference histogram and the current histogram and, (2) when the similarity metric is greater than a threshold value, applying weighted prediction during a motion estimation portion of an encoding of the video stream. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A disclosed method may include storing, within a hardware memory device included as part of a rate—distortion optimization (RDO) hardware pipeline, at least one transform unit table that (1) is pregenerated from a seed probability table for transformation of video data in accordance with a video encoding standard, (2) corresponds to a transform operation supported by the video encoding standard, and (3) corresponds to a transform unit included in the RDO hardware pipeline. The method may also include determining, by accessing the transform unit table, an RDO token rate for an encoding of the video data by a hardware video encoding pipeline that includes the RDO hardware pipeline, and selecting, based on the RDO token rate, a transform operation for the encoding of the video data.

Abstract: A disclosed system may include a hardware distortion data pipeline that may include (1) a quantization module that generates a quantized data set, (2) an inverse quantization module that generates, from the quantized data set, an inverse quantized data set by executing an inverse quantization of the quantized data set, and (3) an inverse transformation module that generates an inversely transformed data set by executing an inverse transformation of the inverse quantized data set. The system may also include a hardware determination pipeline that determines a distortion metric based on the inversely transformed data set and the residual frame data set, and a hardware token rate pipeline that determines, based on the quantized data set, a token rate for an encoding of the residual frame data set via a video encoding pipeline. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system comprises a memory storage configured to store at least a portion of a frame of a video and a hardware motion estimation search processing unit configured to perform at least a portion of a motion estimation search for the video for a plurality of different block sizes. The hardware motion estimation search processing unit is configured to perform the motion estimation search using a plurality of source sub-blocks of a first block size to determine a first type of comparison evaluation values for the first block size. A combination of values included in the first type of comparison evaluation values is utilized to determine at least one second type of comparison evaluation values for a second block size, wherein the second block size is larger than the first block size.

Abstract: A disclosed computer-implemented method may include (1) selecting, from a video stream, a reference frame and a current frame, (2) collecting a reference histogram of the reference frame and a current histogram of the current frame, and (3) generating a smoothed reference histogram by applying a smoothing function to at least a portion of the reference histogram. In some examples, the computer-implemented method may also include (1) determining a similarity metric between the smoothed reference histogram and the current histogram and, (2) when the similarity metric is greater than a threshold value, applying weighted prediction during a motion estimation portion of an encoding of the video stream. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system for calculating token rates for video encoding includes a plurality of different probability lookup tables implemented in hardware, wherein each of the probability lookup tables specifically corresponds to a different prediction mode of a video codec. The system includes an application-specific integrated circuit compute unit. For each candidate prediction mode among the different prediction modes, the application-specific integrated circuit is configured to determine a rate distortion cost (RD Cost) for a video. The application-specific integrated circuit is configured to select one of the plurality of different probability lookup tables that corresponds to the candidate prediction mode and use the selected one of the plurality of different probability lookup tables to calculate a corresponding token rate for the candidate prediction mode.

Abstract: A system comprises a source block buffer and a plurality of hardware motion estimation search processing units in communication with the source block buffer. The source block buffer is configured to store at least a portion of a source block of a source frame of a video. The plurality of hardware motion estimation search processing units are configured to perform at least a portion of a motion estimation for the source block at least in part in parallel across a plurality of different reference frames of the video. Each of the hardware motion estimation search processing units is configured to be assigned a different one of the plurality of different reference frames and is configured to compare at least the portion of the source block with a portion of the assigned one of the different reference frames.

Abstract: The disclosed may include various systems and methods for improving the efficiency and scalability of large-scale systems. For example, the disclosed may include systems and methods for automatic privacy enforcement using privacy-aware infrastructure, scalable general-purpose low cost integer motion search, efficient scaler filter coefficients layout for flexible scaling quality control with limited hardware resources, hardware optimization for power saving with both different codecs enabled, optimizing storage overhead and performance for large distributed data warehouse, mass and volume efficient integration of intersatellite link terminals to a satellite bus, and overcoming retention limit for memory-based distributed database systems.

Abstract: An apparatus includes a first memory interface circuit and a decompression circuit coupled to the first memory interface circuit. The decompression circuit may be configured to (i) receive a reduced size representation of a coding block of data comprising a first bit map, a second bit map, and zero or more non-zero values from an external memory via the first memory interface circuit, (ii) losslessly restore the coding block of data from the reduced size representation of the coding block using the first bit map, the second bit map, and the zero or more non-zero values, and (iii) transfer the restored coding block of data to a processing circuit.

Abstract: An apparatus includes a first memory interface circuit, a second memory interface circuit, and a compression circuit coupled between the first memory interface circuit and the second memory interface circuit. The compression circuit may be configured to receive a coding block of data via the first memory interface circuit, generate a reduced size representation of the coding block, and write the reduced size representation of the coding block to an external memory using the second memory interface circuit. The reduced size representation of said coding block generally comprises a first bit map, a second bit map, and zero or more non-zero values.

Abstract: A dynamic random access memory (DRAM) and a production method, a semiconductor packaging component and a packaging method. The production method comprises: providing a memory wafer, the memory wafer being provided with a memory bare chip which is provided with a top metal layer which is provided with a power source bonding pad, a signal bonding pad, and a micro bonding pad, and an internal bus led out of the memory bare chip being electrically connected to the micro bonding pad; repairing the memory wafer; if a yield of the memory wafer is greater than or equal to a preset threshold, rearranging the micro bonding pad to form a butt-joint bonding pad which is electrically connected to the micro bonding pad and the power source bonding pad. A structure of the DRAM is not significantly changed, a data bandwidth of the DRAM is increased, and a high yield is ensured.

Abstract: A dynamic random access memory (DRAM) and a production method, a semiconductor packaging component and a packaging method. The production method of the DRAM comprises: providing a memory wafer, the memory wafer being provided with a memory bare chip, and the memory bare chip being provided with a top metal layer, the top metal layer being provided with a power source bonding pad, a signal bonding pad, and a micro bonding pad, and an internal bus led out of the memory bare chip being electrically connected to the micro bonding pad; repairing the memory wafer; if a yield of the memory wafer is greater than or equal to a preset threshold, rearranging the micro bonding pad to form a butt joint bonding pad, the butt joint bonding pad being electrically connected to the micro bonding pad and the power source bonding pad.

Abstract: Devices, systems, methods, and other embodiments associated with decoding image data are described. In one embodiment, an apparatus decoding a bitstream includes a parser that parses a command that includes instructions for decoding a syntax element bitstream from the bitstream. The parser functions to identify a number times to repeat the command and to identify a table associated with the syntax element bitstream based, at least in part, on a table identification (ID) in the command. A decoder decodes the syntax element bitstream as specified by the command based, at least in part, on retrieving a value in a table associated with the table ID to generate a syntax element.

Abstract: Devices, systems, methods, and other embodiments associated with a buffer controller are described. In one embodiment, an apparatus includes a buffer to buffer data. The apparatus further includes a status register and control logic. The control logic at least processes write commands. When the buffer is full and a write command to write data to the buffer is received, the control logic is configured to: accept the data without writing the data to the buffer, send an acknowledgment that the buffer was written, and set an overflow bit in the status register.

Abstract: The present specification describes techniques and apparatus that enable synchronization using agent-based semaphores. In one or more implementations, a semaphore is used for a first agent to notify a second agent that the first agent has completed a particular task of a set of tasks and has completed using a shared resource for the particular task.