Abstract: Transmit-side equalization is disclosed for network devices and network communications methods employing onboard/co-packaged optics. An illustrative network device includes a substrate having a host device IC (integrated circuit) and an optical module IC connected by a short-reach link. The optical module IC having a transmit chain includes a CTLE (continuous time linear equalizer) to at least partly compensate for a channel response of the short-reach link, and a driver that amplifies an output of the CTLE for a photoemitter that couples to an optical fiber.

Abstract: Disclosed retimer modules and methods enable equalizer training during link speed negotiation. One illustrative retimer module includes: an analog to digital converter that uses a sampling clock to digitize a receive signal; an equalizer that converts the digitized receive signal into an equalized signal; a decision element that derives a receive symbol stream from the equalized signal; and a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed.

Abstract: An illustrative digital communications method includes: filtering a receive signal to provide a filtered receive signal; deriving symbol decisions from the filtered receive signal; detecting a baud rate of the receive signal; adapting one or more coefficients of the filter if the baud rate is above a predetermined rate; and inhibiting coefficient adaptation if the baud rate is below the predetermined rate. The method may be implemented in a receiver having: a filter to convert a receive signal into a filtered receive signal; a decision element coupled to the filter to derive symbol decisions; a baud rate detector to detect a baud rate of the receive signal; and an adaptation module to adapt one or more coefficients of the filter if the baud rate is above a predetermined rate, the baud rate detector inhibiting adaptation if the baud rate is below the predetermined rate.

Abstract: An illustrative digital communications method includes: filtering a receive signal to provide a filtered receive signal; deriving symbol decisions from the filtered receive signal; detecting a baud rate of the receive signal; adapting one or more coefficients of the filter if the baud rate is above a predetermined rate; and inhibiting coefficient adaptation if the baud rate is below the predetermined rate. The method may be implemented in a receiver having: a filter to convert a receive signal into a filtered receive signal; a decision element coupled to the filter to derive symbol decisions; a baud rate detector to detect a baud rate of the receive signal; and an adaptation module to adapt one or more coefficients of the filter if the baud rate is above a predetermined rate, the baud rate detector inhibiting adaptation if the baud rate is below the predetermined rate.

Abstract: Digital filters and filtering methods may employ truncation, internal rounding, and/or approximation in a summation circuit that combines multiple sets of bit products arranged by bit weight. One illustrative digital filter includes: a summation circuit coupled to multiple partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summation circuit produces a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple partial product circuits into bits for two addends. The CSA tree has multiple lanes of adders, each lane being associated with a corresponding bit weight. The adders in one or more of the lanes associated with least significant bits of the filter output are approximate adders that trade accuracy for simpler implementation.

Abstract: Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.

Abstract: Digital filters and filtering methods may employ truncation, internal rounding, and/or approximation in a summation circuit that combines multiple sets of bit products arranged by bit weight. One illustrative digital filter includes: a summation circuit coupled to multiple partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summation circuit produces a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple partial product circuits into bits for two addends. The CSA tree has multiple lanes of adders, each lane being associated with a corresponding bit weight. The adders in one or more of the lanes associated with least significant bits of the filter output are approximate adders that trade accuracy for simpler implementation.

Abstract: A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.

Abstract: A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.

Abstract: Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.

Abstract: In one illustrative embodiment, an equalizer includes: a shift register, an array of multipliers, an array of multiplexers, and a summer. The shift register provides receive signal samples at each tap. Each multiplier in the array multiplies one of said receive signal samples by a respective coefficient to produce a product, with at least one of said multipliers coupled to a fixed tap. Each multiplexer in the array supplies an associated one of said multipliers with a receive signal sample from a selectable tap. The summer sums the products to produce a filtered output signal. To reduce hardware requirements, coefficient multipliers may be multiplexed to a reduced set of taps, and the dynamic range of the coefficients may be increased by overlapping the sets for different multipliers. Methods of tap selection and coefficient adaptation are disclosed.

Abstract: In one illustrative embodiment, an equalizer includes: a shift register, an array of multipliers, an array of multiplexers, and a summer. The shift register provides receive signal samples at each tap. Each multiplier in the array multiplies one of said receive signal samples by a respective coefficient to produce a product, with at least one of said multipliers coupled to a fixed tap. Each multiplexer in the array supplies an associated one of said multipliers with a receive signal sample from a selectable tap. The summer sums the products to produce a filtered output signal. To reduce hardware requirements, coefficient multipliers may be multiplexed to a reduced set of taps, and the dynamic range of the coefficients may be increased by overlapping the sets for different multipliers. Methods of tap selection and coefficient adaptation are disclosed.

Abstract: An illustrative integrated circuit and method providing on-chip jitter evaluation. One illustrative integrated circuit embodiment includes a digital receiver having a timing recovery circuit that determines a phase offset signal from estimated timing errors of previous sampling instants; and an on-chip memory that captures the phase offset signal, the on-chip memory being coupled to a processor that derives one or more jitter measurements from the phase offset signal. For initial calibration, the processor may configure the receiver for loop back operation, and thereafter the calibration values may enable evaluation of remote transmitter clock jitter.

Abstract: An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.

Abstract: An illustrative SerDes receiver includes: a front-end filter, a precomputation unit, a selection element, and a controller. The front end filter converts a receive signal into a linearly-equalized signal. The precomputation unit accepts the linearly-equalized signal with or without a subtracted feedback signal, and employs a set of comparators with threshold values that depend on a first post-cursor ISI value F1, the set of comparators operating to generate a set of tentative symbol decisions. The selection element derives a selected symbol decision from each set of tentative symbol decisions, thereby deriving a sequence of symbol decisions from the receive signal. The controller constrains F1 if the receive signal uses a PAM4 signal constellation, setting F1 to equal zero if the receive signal is conveyed via a low-loss channel and to equal one if the receive signal is conveyed via a high-loss channel.

Abstract: An illustrative integrated receiver circuit embodiment includes: a set of analog-to-digital converters that sample a receive signal in response to staggered clock signals to provide a parallel set of sampled receive signals; an equalizer that converts the parallel set of sampled receive signals into a parallel set of equalized signals; one or more quantizers that derives symbol decisions from the parallel set of equalized signals; a digital timing circuit that generates the staggered clock signals based on the parallel set of equalized signals; and a clock skew adjustment circuit that provides a controllable skew of at least one of said staggered clock signals relative to at least one other of the staggered clock signals. A monitor circuit is included to provide a reliability indicator for the symbol decisions, as is a controller that determines a dependence of the reliability indicator on the controllable skew.

Abstract: Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.

Abstract: An illustrative SerDes receiver includes: a front-end filter, a precomputation unit, a selection element, and a controller. The front end filter converts a receive signal into a linearly-equalized signal. The precomputation unit accepts the linearly-equalized signal with or without a subtracted feedback signal, and employs a set of comparators with threshold values that depend on a first post-cursor ISI value F1, the set of comparators operating to generate a set of tentative symbol decisions. The selection element derives a selected symbol decision from each set of tentative symbol decisions, thereby deriving a sequence of symbol decisions from the receive signal. The controller constrains F1 if the receive signal uses a PAM4 signal constellation, setting F1 to equal zero if the receive signal is conveyed via a low-loss channel and to equal one if the receive signal is conveyed via a high-loss channel.

Abstract: Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.

Abstract: A receiver embodiment has an equalizer that includes: an array of sample and hold elements, an array of linear equalizers, and an array of decision elements. Each sample and hold element in the array periodically samples an analog receive signal with a respective phase to provide an associated held signal. Each linear equalizer in the array forms a periodically-updated weighted sum of the held signals from the array of sample and hold elements. Each decision element in the array derives at least one sequence of symbol decisions based on at least one of the periodically-updated weighted sums. The resulting sequences of symbol decisions are output in parallel.