Patents by Inventor Junqing Zhou
Junqing Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11674152Abstract: Provided is a novel anti-armyworm use of cry1Ab/cry1AcZM gene. Said gene can be used for controlling or killing Mythimna separate (Walker) and reducing injury to plants by Mythimna separate.Type: GrantFiled: February 2, 2019Date of Patent: June 13, 2023Inventors: Xianbin Hou, Rongjian Ye, Qiuming She, Yu Han, Zhiguo Han, Qiao Yang, Wei Huang, Qianqian Yang, Yanlin Hu, Jicui An, Yingli Wang, Yazhou Yang, Junqing Zhou, Wanggen Zhang
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Publication number: 20210017536Abstract: Provided is a novel anti-armyworm use of cry1Ab/cry1AcZM gene. Said gene can be used for controlling or killing Mythimna separate (Walker) and reducing injury to plants by Mythimna separate.Type: ApplicationFiled: February 2, 2019Publication date: January 21, 2021Applicant: CHINA NATIONAL SEED GROUP CORPORATION, LTD.Inventors: XIANBIN HOU, RONGJIAN YE, QIUMING SHE, YU HAN, ZHIGUO HAN, QIAO YANG, WEI HUANG, QIANQIAN YANG, YANLIN HU, JICUI AN, YINGLI WANG, YAZHOU YANG, JUNQING ZHOU, WANGGEN ZHANG
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Publication number: 20170221754Abstract: An apparatus includes a housing, a chamber disposed in the housing and configured to receive a substrate, a shower head disposed outside the housing and configured to supply a process gas to the chamber, and a hot wire at a first temperature disposed between the shower head and the substrate. The hot wire at the first temperature ionizes the process gas, and the ionized gas is supplied to the substrate for performing a hot-wire assisted plasma-assisted pre-cleaning process and a hot-wire assisted atomic layer deposition process. The apparatus also includes a hot plate in the chamber and configured to bring the substrate to a second temperature.Type: ApplicationFiled: January 9, 2017Publication date: August 3, 2017Inventors: GUANGJIE YUAN, JUNQING ZHOU, HAIYANG ZHANG
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Patent number: 9410233Abstract: A method of manufacturing semiconductor device and a wafer are provided in accordance with embodiments of the present invention, which relates to semiconductor technology. The method includes: providing a substrate, and forming a gate oxide layer and a polysilicon layer on a first surface of the substrate; etching the polysilicon layer by use of a patterned mask so as to form a polysilicon gate with reentrants; depositing a tensile stress film on a second surface of the substrate before etching the polysilicon layer. The tensile stress film can be deposited on the second surface of the substrate for generating the tensile stress for the wafer. Thus, a polysilicon gate with reentrants can be formed in etching process. In this way, semiconductor devices can have smaller gate-source/drain overlap capacitance and better TDDB parameters, and the performance of the devices can be improved.Type: GrantFiled: September 23, 2011Date of Patent: August 9, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Xiaoying Meng, Junqing Zhou, Haiyang Zhang
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Patent number: 9064819Abstract: This disclosure relates to a post-etch treating method. An opening is formed by etching a stacked structure of a dielectric layer, an intermediate layer and a metal hard mask layer arranged in order from bottom to top. The treating method sequentially comprises steps of: performing a first cleaning process on the stacked structure with the opening so as to remove at least a part of the metal hard mask layer; and performing a second cleaning process on the stacked structure with the opening so as to remove etching residues.Type: GrantFiled: December 7, 2011Date of Patent: June 23, 2015Assignee: Semiconductor Manufacturing Internation (Beijing) CorporationInventors: Haiyang Zhang, Minda Hu, Junqing Zhou, Dongjiang Wang
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Patent number: 8828871Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.Type: GrantFiled: November 10, 2011Date of Patent: September 9, 2014Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Junqing Zhou, Xiaoying Meng, Haiyang Zhang
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Patent number: 8753930Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.Type: GrantFiled: December 14, 2011Date of Patent: June 17, 2014Assignee: Semiconductor Manufacturing (Shanghai) CorporationInventors: Xiaoying Meng, Junqing Zhou, Haiyang Zhang
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Patent number: 8445376Abstract: A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the lower interconnecting layer on a substrate, and forming the upper interconnecting layer on the lower interconnecting layer. The lower interconnecting layer includes a first dielectric layer, a plurality of wire trenches formed in the first dielectric layer and being filled with copper, and a first top barrier layer overlying the first dielectric layer and the wire trenches. The upper interconnecting layer includes a second dielectric layer on the top barrier layer, and a plurality of vias extending through the second dielectric layer and the top barrier layer and exposing the copper in the wire trenches. The method further includes treating the exposed copper using a plasma process comprising NH3.Type: GrantFiled: November 23, 2011Date of Patent: May 21, 2013Assignee: Semiconductor Manufacturing International Corp.Inventors: Dongjiang Wang, Junqing Zhou, Haiyang Zhang
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Publication number: 20130095657Abstract: This disclosure relates to a post-etch treating method. An opening is formed by etching a stacked structure of a dielectric layer, an intermediate layer and a metal hard mask layer arranged in order from bottom to top. The treating method sequentially comprises steps of: performing a first cleaning process on the stacked structure with the opening so as to remove at least a part of the metal hard mask layer; and performing a second cleaning process on the stacked structure with the opening so as to remove etching residues.Type: ApplicationFiled: December 7, 2011Publication date: April 18, 2013Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: HAIYANG ZHANG, Minda Hu, Junqing Zhou, Dongjiang Wang
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Publication number: 20130059438Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.Type: ApplicationFiled: November 10, 2011Publication date: March 7, 2013Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: JUNQING ZHOU, XIAOYING MENG, HAIYANG ZHANG
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Publication number: 20120289017Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.Type: ApplicationFiled: December 14, 2011Publication date: November 15, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: XIAOYING MENG, Junqing Zhou, Haiyang Zhang
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Publication number: 20120276737Abstract: A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the lower interconnecting layer on a substrate, and forming the upper interconnecting layer on the lower interconnecting layer. The lower interconnecting layer includes a first dielectric layer, a plurality of wire trenches formed in the first dielectric layer and being filled with copper, and a first top barrier layer overlying the first dielectric layer and the wire trenches. The upper interconnecting layer includes a second dielectric layer on the top barrier layer, and a plurality of vias extending through the second dielectric layer and the top barrier layer and exposing the copper in the wire trenches. The method further includes treating the exposed copper using a plasma process comprising NH3.Type: ApplicationFiled: November 23, 2011Publication date: November 1, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: DONGJIANG WANG, Junqing Zhou, Haiyang Zhang
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Publication number: 20120273923Abstract: A method of manufacturing semiconductor device and a wafer are provided in accordance with embodiments of the present invention, which relates to semiconductor technology. The method includes: providing a substrate, and forming a gate oxide layer and a polysilicon layer on a first surface of the substrate; etching the polysilicon layer by use of a patterned mask so as to form a polysilicon gate with reentrants; depositing a tensile stress film on a second surface of the substrate before etching the polysilicon layer. The tensile stress film can be deposited on the second surface of the substrate for generating the tensile stress for the wafer. Thus, a polysilicon gate with reentrants can be formed in etching process. In this way, semiconductor devices can have smaller gate-source/drain overlap capacitance and better TDDB parameters, and the performance of the devices can be improved.Type: ApplicationFiled: September 23, 2011Publication date: November 1, 2012Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Xiaoying Meng, Junqing Zhou, Haiyang Zhang