Abstract: The present invention relates to a process for preparing catalytic anodes for use in electro-chlorination systems which generate chlorine from aqueous solutions via the chlorine evolution reaction. These anodes comprise an electrically conductive metallurgical layer essentially comprising ruthenium, tin and titanium. The desired characteristics of this metallurgical layer may be realised via a process of preparation employing specific control of reactants and process conditions.

Abstract: A computing system includes: a host configured to provide data and address information on the data; and a memory system configured to store the data, wherein the memory system comprises: a plurality of memory devices configured to be grouped into at least one memory device group; and a controller configured to control each of the plurality of memory devices, wherein the controller comprises: a group setter configured to set the memory device groups with respect to a type of the data by a request of the host; and a processor configured to read the data from, or write the data to, the memory device group corresponding to the type of the data.

Abstract: The present invention relates to technology for preparing oligonucleotides for detecting a target nucleic acid molecule in a sample. Unlike the conventional methods, the present invention provides a first oligonucleotide candidate group designed appropriately for the first selected nucleotide sequence of the target nucleic acid molecule as a standard instead of simultaneously referring to all of the sequences exhibiting the genetic diversity. Then, an optimal oligonucleotide capable of accurately detecting a target nucleic acid molecule exhibiting genetic diversity in a sample is provided by using the first oligonucleotide candidate group.

Abstract: A memory system may include: one or more normal memory regions; one or more spare memory regions; and a controller suitable for controlling the normal memory regions and the spare memory regions. The controller may determine, among the normal memory regions, a first normal cell region that includes a concentrated cell region whose access count exceeds a first threshold and neighboring cell regions in a set range from the concentrated cell region perform first address mapping to map an address of the first normal cell region to an address of a first spare cell region in the spare memory regions, and perform second address mapping to map the address of the first spare cell region to an address of a second normal cell region in the normal memory regions, when an access count of the first spare cell region exceeds a second threshold.

Abstract: A computing system includes: a host configured to provide data and address information on the data; and a memory system configured to store the data, wherein the memory system comprises: a plurality of memory devices configured to be grouped into at least one memory device group; and a controller configured to control each of the plurality of memory devices, wherein the controller comprises: a group setter configured to set the memory device groups with respect to a type of the data by a request of the host; and a processor configured to read the data from, or write the data to, the memory device group corresponding to the type of the data.

Abstract: A computing system includes: a host configured to provide data and address information on the data; and a memory system configured to store the data, wherein the memory system comprises: a plurality of memory devices configured to be grouped into at least one memory device group; and a controller configured to control each of the plurality of memory devices, wherein the controller comprises: a group setter configured to set the memory device groups with respect to a type of the data by a request of the host; and a processor configured to read the data from, or write the data to, the memory device group corresponding to the type of the data.

Abstract: A memory system may include: a memory pool including a plurality of memory regions; and a controller suitable for controlling the memory pool, wherein each of the memory regions includes one or more row groups, each row group having a predetermined row group size, and wherein the controller counts the numbers of row accesses to the respective memory regions, determines row group sizes according to the row access counts of the respective memory regions, increases a representative access count of a row group including a certain row when the row is accessed, and provides a command to the memory pool to perform a target refresh operation on a target row group whose representative access count exceeds a threshold value.

Abstract: The memory system includes a memory device including a volatile storage area and a non-volatile storage area; and a controller including first and second interfaces for transferring data between the memory system and a host, and suitable for transferring data between the volatile storage area and the host through the first interface and transferring data between the non-volatile storage area and the host through the second interface, wherein the controller is further suitable for determining whether or not an error occurs in data read from the volatile storage area in a normal operation mode, and dumping a whole of the volatile storage area into a predetermined first location of the non-volatile storage area when an error is determined to occur in the data read from the volatile storage area.

Abstract: A memory system may include: a memory pool including a plurality of memory regions; and a controller suitable for controlling the memory pool, wherein each of the memory regions includes one or more row groups, each row group having a predetermined row group size, and wherein the controller counts the numbers of row accesses to the respective memory regions, determines row group sizes according to the row access counts of the respective memory regions, increases a representative access count of a row group including a certain row when the row is accessed, and provides a command to the memory pool to perform a target refresh operation on a target row group whose representative access count exceeds a threshold value.

Abstract: A memory system may include: one or more normal memory regions; one or more spare memory regions; and a controller suitable for controlling the normal memory regions and the spare memory regions. The controller may determine, among the normal memory regions, a first normal cell region that includes a concentrated cell region whose access count exceeds a first threshold and neighboring cell regions in a set range from the concentrated cell region perform first address mapping to map an address of the first normal cell region to an address of a first spare cell region in the spare memory regions, and perform second address mapping to map the address of the first spare cell region to an address of a second normal cell region in the normal memory regions, when an access count of the first spare cell region exceeds a second threshold.

Abstract: A memory system includes: a non-volatile memory device for including a first storage region and a second storage region; and a controller for including first and second interfaces for inputting/outputting a data to/from a host, inputting/outputting a first data of the first storage region through the first interface, and inputting/outputting a second data of the second storage region through the second interface, wherein when the first data is programmed in the first storage region, the controller detects a value of the first data, selectively inverts the value of the first data based on the detection result, and program a resultant value, and when the second data is programmed in the second storage region, the controller detects a state of the second storage region where the second data is programmed, selectively inverts a value of the second data based on the state detection result, and program a resultant value.

Abstract: A memory system includes: a nonvolatile memory device including first and second storage regions; and a controller including first and second interfaces, the first interface being suitable for exchanging data between the first storage region and a host, and the second interface being suitable for exchanging data between the second storage region and the host.

Abstract: A computing system includes: a host configured to provide data and address information on the data; and a memory system configured to store the data, wherein the memory system comprises: a plurality of memory devices configured to be grouped into at least one memory device group; and a controller configured to control each of the plurality of memory devices, wherein the controller comprises: a group setter configured to set the memory device groups with respect to a type of the data by a request of the host; and a processor configured to read the data from, or write the data to, the memory device group corresponding to the type of the data.

Abstract: The present invention relates to technology for preparing oligonucleotides for detecting a target nucleic acid molecule in a sample. Unlike the conventional methods, the present invention provides a first oligonucleotide candidate group designed appropriately for the first selected nucleotide sequence of the target nucleic acid molecule as a standard instead of simultaneously referring to all of the sequences exhibiting the genetic diversity. Then, an optimal oligonucleotide capable of accurately detecting a target nucleic acid molecule exhibiting genetic diversity in a sample is provided by using the first oligonucleotide candidate group.

Abstract: The memory system includes a memory device including a volatile storage area and a non-volatile storage area; and a controller including first and second interfaces for transferring data between the memory system and a host, and suitable for transferring data between the volatile storage area and the host through the first interface and transferring data between the non-volatile storage area and the host through the second interface, wherein the controller is further suitable for determining whether or not an error occurs in data read from the volatile storage area in a normal operation mode, and dumping a whole of the volatile storage area into a predetermined first location of the non-volatile storage area when an error is determined to occur in the data read from the volatile storage area.

Abstract: A memory system includes: a non-volatile memory device for including a first storage region and a second storage region; and a controller for including first and second interfaces for inputting/outputting a data to/from a host, inputting/outputting a first data of the first storage region through the first interface, and inputting/outputting a second data of the second storage region through the second interface, wherein when the first data is programmed in the first storage region, the controller detects a value of the first data, selectively inverts the value of the first data based on the detection result, and program a resultant value, and when the second data is programmed in the second storage region, the controller detects a state of the second storage region where the second data is programmed, selectively inverts a value of the second data based on the state detection result, and program a resultant value.

Abstract: A memory system includes: a nonvolatile memory device; and a controller operatively coupled to the nonvolatile memory device and to a host, the controller including first and second interfaces suitable for inputting and/or outputting data from or to the host, wherein the controller is suitable for selecting any one of the first and second interfaces depending on a result of a durability check of the nonvolatile memory device.

Abstract: A memory system includes: a nonvolatile memory device including first and second storage regions; and a controller including first and second interfaces, the first interface being suitable for exchanging data between the first storage region and a host, and the second interface being suitable for exchanging data between the second storage region and the host.

Abstract: A memory system includes: a nonvolatile memory device; and a controller operatively coupled to the nonvolatile memory device and to a host, the controller including first and second interfaces suitable for inputting and/or outputting data from or to the host, wherein the controller is suitable for selecting any one of the first and second interfaces depending on a result of a durability check of the nonvolatile memory device.

Abstract: A system and method for controlling congestion using Request-to-Send (RTS) and Clear-to-Send (CTS) in a wireless mesh network are provided. A receiver in a congestion state sets a duration field value of congestion control in a CTS frame and transmits the CTS frame to a sender. In response, the sender retransmits an RTS frame to the receiver without transmitting data, after waiting for an RTS retransmission waiting time period corresponding to the duration field value. The congestion state information is broadcast to neighboring nodes. Therefore, the congestion control system using the CTS frame does not use a separate frame for the congestion control. And, all of the neighboring nodes can participate in the congestion control, increasing the network efficiency.