Abstract: A data driver includes a shift register block which generates enable signals based on a data clock signal, a gating signal generating block which generates gating signals, a data transmission block including data gating circuits which receives a data signal and transmits the data signal to a latch block, and the latch block which stores the data signal based on the enable signals. Each of the data gating circuits includes data transmission paths and determines a target transmission path, which transmits the data signal to the latch block, among the data transmission paths based on the gating signals.

Abstract: A data driver of a display device includes first through N-th data latches, where N is an integer greater than 1, first through (N+1)-th channel circuits, a first multiplexer connected between the first through N-th data latches and the first through (N+1)-th channel circuits, and a second multiplexer connected between the first through (N+1)-th channel circuits and first through N-th data lines. In a first period, the first multiplexer connects the first through N-th data latches to the first through N-th channel circuits, respectively, and the second multiplexer connects the first through N-th data lines to the first through N-th channel circuits, respectively. In a second period, the first multiplexer connects the first through N-th data latches to second through (N+1)-th channel circuits, respectively, and the second multiplexer connects the first through N-th data lines to the second through (N+1)-th channel circuits, respectively.

Abstract: A data driving circuit of a display device includes a digital-analog converter which includes a gamma reference voltage generator to output gamma reference voltages in response to a first-group signal of a digital signal, and a voltage selector to output, as a gamma selection voltage, one of the gamma reference voltages in response to a second-group signal of the digital signal. The data driving circuit also includes a first amplifier to receive the gamma selection voltage and to output a first conversion voltage, a boosting circuit to convert the first conversion voltage into a second conversion voltage in response to the first-group signal of the digital signal, and a second amplifier to receive the second conversion voltage and to output an analog signal.

Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.

Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.