Patents by Inventor Juntan Zhang

Juntan Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Family of LDPC codes for video broadcasting applications
    Patent number: 8689092
    Abstract: A family of quasi cyclic irregular low density parity check codes for video broadcasting applications. The parity check matrices of the constructed low density parity check codes have quasi-cyclic structures to facilitate hardware implementation and have proper check/bit degree distributions to offer frame error rate performance lower than 10?7.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: April 1, 2014
    Assignee: Availink, Inc.
    Inventors: Fengwen Sun, Ming Yang, Juntan Zhang, Yuhai Shi
  • Bit mapping scheme for an LDPC coded 32APSK system
    Patent number: 8369448
    Abstract: A digital communication system, having a transmitter to transmit a digital signal; and a receiver to receive the digital signal; wherein the digital signal utilizes a 32APSK system with FEC coding, and the signal is bit-mapped using gray mapping, and bits of the digital signal are ordered based on the values of a log likelihood ratio from a communications channel.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: February 5, 2013
    Assignee: Availink, Inc.
    Inventors: Juntan Zhang, Fengwen Sun
  • Interleaving scheme for an LDPC coded 32 APSK system
    Patent number: 8301960
    Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in 32APSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: October 30, 2012
    Assignee: Availink, Inc.
    Inventors: Juntan Zhang, Zhiyong Wu, Peng Gao, Fengwen Sun
  • Interleaving scheme for an LDPC coded QPSK/8PSK system
    Patent number: 8230299
    Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in QPSK/8PSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: July 24, 2012
    Assignee: Availink, Inc.
    Inventors: Ming Yang, Juntan Zhang, Zhiyong Wu, Fengwen Sun
  • FAMILY OF LDPC CODES FOR VIDEO BROADCASTING APPLICATIONS
    Publication number: 20110307754
    Abstract: A family of quasi cyclic irregular low density parity check codes for video broadcasting applications. The parity check matrices of the constructed low density parity check codes have quasi-cyclic structures to facilitate hardware implementation and have proper check/bit degree distributions to offer frame error rate performance lower than 10?7.
    Type: Application
    Filed: September 18, 2006
    Publication date: December 15, 2011
    Inventors: Fengwen Sun, Ming Yang, Juntan Zhang, Yuhai Shi
  • INTERLEAVING SCHEME FOR AN LDPC CODED QPSK/8PSK SYSTEM
    Publication number: 20110258521
    Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in QPSK/8PSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
    Type: Application
    Filed: March 1, 2010
    Publication date: October 20, 2011
    Applicant: AVAILINK, INC.
    Inventors: Ming Yang, Juntan Zhang, Zhiyong Wu, Fengwen Sun
  • Interleaving scheme for an LDPC coded 16APSK system
    Patent number: 8028219
    Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in 16ASPK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: September 27, 2011
    Assignee: Availink, Inc.
    Inventors: Juntan Zhang, Peng Gao, Fengwen Sun
  • INTERLEAVING SCHEME FOR AN LDPC CODED 32 APSK SYSTEM
    Publication number: 20110202814
    Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in 32APSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
    Type: Application
    Filed: February 22, 2010
    Publication date: August 18, 2011
    Applicant: AVAILINK, INC.
    Inventors: Juntan Zhang, Zhiyong Wu, Peng Gao, Fengwen Sun
  • BIT MAPPING SCHEME FOR AN LDPC CODED 16APSK SYSTEM
    Publication number: 20110173509
    Abstract: A digital communication system, having a transmitter to transmit a digital signal; and a receiver to receive the digital signal; wherein the digital signal utilizes a 16APSK system, and the signal is bit-mapped using gray mapping, and bits of the digital signal are ordered based on the values of a log likelihood ratio from a communications channel.
    Type: Application
    Filed: March 4, 2010
    Publication date: July 14, 2011
    Applicant: AVAILINK, INC.
    Inventors: Juntan Zhang, Xunchun Li, Fengwen Sun
  • BIT MAPPING SCHEME FOR AN LDPC CODED 32APSK SYSTEM
    Publication number: 20110164705
    Abstract: A digital communication system, having a transmitter to transmit a digital signal; and a receiver to receive the digital signal; wherein the digital signal utilizes a 32APSK system with FEC coding, and the signal is bit-mapped using gray mapping, and bits of the digital signal are ordered based on the values of a log likelihood ratio from a communications channel.
    Type: Application
    Filed: September 18, 2006
    Publication date: July 7, 2011
    Inventors: Juntan Zhang, Jilong Li, Fengwen Sun
  • INTERLEAVING SCHEME FOR AN LDPC CODED 16 APSK SYSTEM
    Publication number: 20110107183
    Abstract: An approach is provided for interleaving low density parity check (LDPC) encoded bits in 16ASPK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
    Type: Application
    Filed: September 18, 2006
    Publication date: May 5, 2011
    Inventors: Juntan Zhang, Peng Gao, Fengwen Sun
  • 2D-normalized min-sum decoding for ECC codes
    Patent number: 7562279
    Abstract: A method for decoding error-correcting codes normalizes messages generated by a bit node processor, and normalizes messages generated by the check node processor.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: July 14, 2009
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Juntan Zhang, Daqing Gu, Jinyun Zhang
  • Combined-replica group-shuffled iterative decoding for error-correcting codes
    Patent number: 7373585
    Abstract: A method generates a combined-replica group-shuffled iterative decoder. First, an error-correcting code and an iterative decoder for an error-correcting code is received. Multiple group-shuffled sub-decoders for the error-correcting code are constructed, based on the iterative decoder. Then, the multiple group-shuffled sub-decoders are combined into a combined-replica group-shuffled iterative decoder.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: May 13, 2008
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Jonathan S. Yedidia, Marc P. C. Fossorier, Juntan Zhang, Yige Wang
  • 2D-normalized min-sum decoding for ECC codes
    Publication number: 20060282742
    Abstract: A method for decoding error-correcting codes normalizes messages generated by a bit node processor, and normalizes messages generated by the check node processor.
    Type: Application
    Filed: May 20, 2005
    Publication date: December 14, 2006
    Inventors: Juntan Zhang, Daqing Gu, Jinyun Zhang
  • Combined-replica group-shuffled iterative decoding for error-correcting codes
    Publication number: 20060161830
    Abstract: A method generates a combined-replica group-shuffled iterative decoder, comprising. First. an error-correcting code and an iterative decoder for an error-correcting code is received by the method. Multiple group-shuffled sub-decoders for the error-correcting code are constructed, based on the iterative decoder. Then, the multiple group-shuffled sub-decoders are combined into a combined-replica group-shuffled iterative decoder.
    Type: Application
    Filed: January 14, 2005
    Publication date: July 20, 2006
    Inventors: Jonathan Yedidia, Marc Fossorier, Juntan Zhang, Yige Wang