Patents by Inventor Junting Liu-Norrod

Junting Liu-Norrod has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200066513
    Abstract: Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Manuj Nahar, Darwin Franseda Fan, Junting Liu-Norrod, Michael Mutch
  • Patent number: 8735292
    Abstract: Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Junting Liu-Norrod, Er-Xuan Ping, Seiichi Takedai
  • Publication number: 20130237056
    Abstract: Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.
    Type: Application
    Filed: April 8, 2013
    Publication date: September 12, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Junting Liu-Norrod, Er-Xuan Ping, Seiichi Takedai