Abstract: A semiconductor memory device is configured to internally perform a test operation utilizing a random data pattern. The semiconductor memory device includes a random data pattern test unit that operates under control of on-board control logic that also manages normal operation of the semiconductor memory device. The control logic controls test operation of the semiconductor memory device in response to simple commands received from an external device. Therefore, the test time may be reduced more than when a test is entirely controlled by an external device. Furthermore, since the external device does not need to manage the random data pattern, the test cost may be reduced more than when a test is performed under control of the external device.

Abstract: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, the semiconductor apparatus may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of a voltage control code, a voltage comparison unit configured to compare a voltage level of a target voltage with a voltage level of the internal voltage, and a voltage control code generation unit configured to adjust the code value of the voltage control code based on the comparison result of the voltage comparison unit.

Abstract: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, the semiconductor apparatus may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of a voltage control code, a voltage comparison unit configured to compare a voltage level of a target voltage with a voltage level of the internal voltage, and a voltage control code generation unit configured to adjust the code value of the voltage control code based on the comparison result of the voltage comparison unit.