Patents by Inventor Junwei Hu

Junwei Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984915
    Abstract: Example temperature compensation circuits and a phased array apparatus are described. One example temperature compensation circuit is applied to a signal processing path. The example temperature compensation circuit includes a temperature detection circuit, a temperature conversion circuit, and a passive variable attenuator. The passive variable attenuator is configured to be connected in series in the signal processing path. The temperature detection circuit is configured to generate a temperature signal and a reference signal, and output the temperature signal and the reference signal to the temperature conversion circuit. The temperature signal monotonically changes with a temperature of the signal processing path. The temperature conversion circuit is configured to generate a control signal based on the temperature signal and the reference signal.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: May 14, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Junwei Hu, Rong Peng
  • Publication number: 20230366304
    Abstract: The invention relates to the technical field of in-situ development of shale oil resources and consists of a device and technique for simulating the propagation of shale fractures under the influence of high-temperature convective heat. The apparatus is comprised of a data collecting and processing system, a high-temperature thermal fluid generator, a high-pressure pumping device, and a shale reactor. The thermal fluid generator for high temperatures consists of a fluid generator, a temperature controller, and a pressure controller. The shale, reaction kettle consists of an outer chamber, an outer chamber lid, a scaled rock cavity, and a shale sample. The outer cavity cover of the reactor is fitted with a simulated wellbore, the bottom end of the simulated wellbore penetrates the inner cavity cover and extends to the interior of the shale sample, and the top of the simulated wellbore is connected to a high-pressure constant-speed injection pump.
    Type: Application
    Filed: January 4, 2023
    Publication date: November 16, 2023
    Applicant: China University of Petroleum (East China)
    Inventors: Chuanjin YAO, Jiao GE, Junwei HU, Liang XU, Qi ZHANG, Lei LI, Kai ZHANG, Jianchun XU
  • Publication number: 20210249790
    Abstract: Example temperature compensation circuits and a phased array apparatus are described. One example temperature compensation circuit is applied to a signal processing path. The example temperature compensation circuit includes a temperature detection circuit, a temperature conversion circuit, and a passive variable attenuator. The passive variable attenuator is configured to be connected in series in the signal processing path. The temperature detection circuit is configured to generate a temperature signal and a reference signal, and output the temperature signal and the reference signal to the temperature conversion circuit. The temperature signal monotonically changes with a temperature of the signal processing path. The temperature conversion circuit is configured to generate a control signal based on the temperature signal and the reference signal.
    Type: Application
    Filed: April 28, 2021
    Publication date: August 12, 2021
    Inventors: Junwei HU, Rong PENG
  • Patent number: 9105647
    Abstract: A semiconductor device has a flipchip semiconductor die mounted to a first substrate using a plurality of first bumps. An opening or plurality of openings is formed in the first substrate in a location central to placement of the flipchip semiconductor die to the first substrate. A plurality of semiconductor die is mounted to a second substrate. The semiconductor die are electrically connected with bond wires. An encapsulant is over the plurality of semiconductor die and second substrate. The second substrate is mounted to the first substrate with a plurality of second bumps. An underfill material is dispensed through the opening in the first substrate between the flipchip semiconductor die and first substrate. The dispensing of the underfill material is discontinued as the underfill material approaches or reaches a perimeter of the flipchip semiconductor die to reduce bleeding of the underfill material. The underfill material is cured.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: August 11, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Junwei Hu, JaeHak Yee, Lin Tan, Wenbin Qu, YuFeng Feng
  • Publication number: 20140018474
    Abstract: Provided are a composition for anti-scratch and wear-resistance properties, a method of preparing the same, and its application. The composition has inorganic particles, a dispersant and an organic binding agent. The inorganic particles are spherical and have an average particle size ranging from 10 nanometers to 999 nanometers. The dispersant has an inorganic dispersant and a polymer dispersant. The specific gravity of the inorganic particles and inorganic dispersant are respectively represented by s1 and s2, 0.05<s2/s1<1. The total amount of inorganic particles and inorganic dispersant ranges from 0.5 to 70 parts by weight, the amount of polymer dispersant ranges from 0.1 to 20 parts by weight, and the amount of organic binding agent ranges from 10 to 98 parts by weight. Since the inorganic particles are stably dispersed in the composition, the composition can be applied to coating, paint or composite materials and has improved wear-resistant and anti-scratch properties.
    Type: Application
    Filed: December 19, 2012
    Publication date: January 16, 2014
    Applicant: ETERNAL CHEMICAL CO., LTD.
    Inventors: Lang Zhou, Huanzhen Shao, Junwei Hu, Qingzhu Zhou, Hung-Yu Wang
  • Publication number: 20110278712
    Abstract: A semiconductor device has a flipchip semiconductor die mounted to a first substrate using a plurality of first bumps. An opening or plurality of openings is formed in the first substrate in a location central to placement of the flipchip semiconductor die to the first substrate. A plurality of semiconductor die is mounted to a second substrate. The semiconductor die are electrically connected with bond wires. An encapsulant is over the plurality of semiconductor die and second substrate. The second substrate is mounted to the first substrate with a plurality of second bumps. An underfill material is dispensed through the opening in the first substrate between the flipchip semiconductor die and first substrate. The dispensing of the underfill material is discontinued as the underfill material approaches or reaches a perimeter of the flipchip semiconductor die to reduce bleeding of the underfill material. The underfill material is cured.
    Type: Application
    Filed: May 17, 2010
    Publication date: November 17, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Junwei Hu, JaeHak Yee, Lin Tan, Wenbin Qu, YuFeng Feng