Abstract: A low power redundancy circuit that has applications in CMOS memories. This circuit employs fuses to select addressing paths and to provide address information of failing memory columns. Path selection is made by rendering a fuse device non-conductive which disconnects a clamping off bias that inhibits conduction through an N-channel transistor and preventing signal flow through the selected addressing paths to the output. Memory column addressing information is generated by selectively rendering a second set of fuses conductive or non-conductive to produce a logical one or zero respectively at the output of the addressing paths. A redundant signal is used to precondition the select circuitry and prevent a transient pulse from propagating through the output of the select circuitry when a section is not activated. The circuit uses CMOS N-channel transistors configured such as to produce low standby power while being able to deliver necessary output signals when path selection is made.