Abstract: An upper semiconductor build has an upper build dielectric; at least two upper build electrical signal contact bonding pads; at least one upper build dummy contact bonding pad; an upper build ground network electrically coupled to the at least two upper build electrical signal contact bonding pads; and an upper build anti-fuse dielectric between the upper build ground network and the upper build dummy contact bonding pad. A lower semiconductor build has a lower build dielectric; at least two lower build electrical signal contact bonding pads; at least one lower build dummy contact bonding pad; a lower build ground network; and a lower build anti-fuse dielectric between the lower build ground network and the lower build dummy contact bonding pad. The two builds are hybrid bonded to each other. When excess charge builds up, the anti-fuse dielectrics are blown and conduct the excess charge to ground.

Abstract: A microelectronics device with anti-counterfeiting measures that includes an integrated circuit packaging and a piezoelectric element embedded on the integrated circuit packaging, such as on the surface of the integrated circuit packaging. The piezoelectric element is configured to generate a unique identification code in response to a series of controlled mechanical stresses being applied to the piezoelectric element. Due to the inherent variability in piezoelectric responses, there is a high degree of uniqueness in the identification code making them extremely difficult for counterfeiters to replicate. Furthermore, by applying different stress sequences, a multitude of unique identification codes can be generated from a single piezoelectric element providing an additional layer of security.

Abstract: Embodiments presented in this disclosure generally relate to anti-counterfeiting in microelectronics. More specifically, embodiments disclosed herein are directed to an integrated circuits (IC) with authenticity validation structures. One embodiment includes an IC, and a molding compound containing the IC, where the molding compound comprises a channel. A mixture is placed within the channel, where the mixture comprises one or more magnetic particles that provide an inductive signature for identifying the package.

Abstract: Embodiments presented in this disclosure generally relate to anti-counterfeiting for integrated circuits (ICs). More specifically, embodiments disclosed herein are directed to an authenticity validation structure integrated within an IC's packaging. One embodiment includes an IC and a metal alloy wire. The metal alloy wire comprises one or more resistive elements, and a total resistance of the one or more resistive elements provides a validation value for the package to ensure the package is authentic.

Abstract: Embodiments of present invention provide a method. The method includes forming a set of metal pillars on a substrate; forming a negative-tone organic dielectric layer covering the set of metal pillars; planarizing the negative-tone organic dielectric layer to expose the set of metal pillars; forming a resist mask on the negative-tone organic dielectric layer, the resist mask having openings that expose the set of metal pillars; and forming a redistribution layer in the openings of the resist mask, the redistribution layer being in direct contact with the set of metal pillars. A structure formed thereby is also provided.

Abstract: A lid for a photonic device includes a resilient frame configured to bridge transversely over one or more optical fibers in a region of the photonic device. The resilient frame includes a span that defines a span direction, the resilient frame further includes end portions that are disposed transversely to the span to form an internal region of the frame. A compliant solid base material is formed within the internal region of the frame and attached to the frame along the span. The resilient frame is configured to transversely span over one or more optical fibers and preload the one or more optical fibers with the compliant solid base material when secured to the photonic device.

Abstract: An image sensor with improved performance is provided. The image sensor includes a substrate, a prism structure on the substrate, the prism structure including at least one nanopattern, and an anti-reflection structure on the prism structure, the anti-reflection structure including at least one opening array, the opening array including a plurality of spaced-apart openings.

Abstract: An organic compound, an organic photoelectric device, an image sensor, and an electronic device, the organic compound being represented by Chemical Formula 1: wherein, in Chemical Formula 1, R1, R2, R3, R4, R5, and R6 are each independently a hydrogen atom, a substituted or unsubstituted C1-C4 alkyl group, a substituted or unsubstituted C1-C4 alkoxy group, or a substituted or unsubstituted C1-C4 alkylthio group, and A is a functional group including a heteroaryl group that includes at least one sulfur atom.

Abstract: An organic photoelectric conversion device and an image sensor, the organic photoelectric conversion device including an upper electrode; a lower electrode; and an active layer between the upper electrode and the lower electrode, wherein the active layer includes bis-(4-dimethylaminodithiobenzyl)-Ni(II) (BDN) and [6,6]-Phenyl-C71-butyric acid methyl ester (PC70BM).

Abstract: An organic compound, an organic photoelectric device, an image sensor, and an electronic device, the organic compound being represented by Chemical Formula 1: wherein, in Chemical Formula 1, R1, R2, R3, R4, R5, and R6 are each independently a hydrogen atom, a substituted or unsubstituted C1-C4 alkyl group, a substituted or unsubstituted C1-C4 alkoxy group, or a substituted or unsubstituted C1-C4 alkylthio group, and A is a functional group including a heteroaryl group that includes at least one sulfur atom.

Abstract: A method of manufacturing a semiconductor package, the method including forming a hole that penetrates an interconnect substrate; providing a first carrier substrate below the interconnect substrate; providing a semiconductor chip in the hole; forming a molding layer by coating a molding composition on the semiconductor chip and the interconnect substrate; adhering a second carrier substrate onto the molding layer with an adhesive layer; removing the first carrier substrate to expose a bottom surface of the semiconductor chip and a bottom surface of the interconnect substrate; forming a redistribution substrate below the semiconductor chip and the interconnect substrate; detaching the second carrier substrate from the adhesive layer; and removing the adhesive layer.

Abstract: A method of manufacturing a semiconductor package, the method including forming a hole that penetrates an interconnect substrate; providing a first carrier substrate below the interconnect substrate; providing a semiconductor chip in the hole; forming a molding layer by coating a molding composition on the semiconductor chip and the interconnect substrate; adhering a second carrier substrate onto the molding layer with an adhesive layer; removing the first carrier substrate to expose a bottom surface of the semiconductor chip and a bottom surface of the interconnect substrate; forming a redistribution substrate below the semiconductor chip and the interconnect substrate; detaching the second carrier substrate from the adhesive layer; and removing the adhesive layer.

Abstract: The inventive concepts provide methods of purifying a block copolymer and methods of forming a pattern using the same. The purifying method is performed using a first adsorbent. The first adsorbent has adsorbability with respect to a first polymer block having a molecular weight equal to or greater than a first average molecular weight. The purifying method further includes purifying a synthesized polymer using a second adsorbent. The second adsorbent interacts with a second polymer block.