Patents by Inventor Jun Woo Jang
Jun Woo Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12248868Abstract: A neural processing device includes a first memory configured to store universal data, a second memory distinguished from the first memory and having a capacity less than that of the first memory, a bandwidth control path configured to reconfigure a memory bandwidth for memory clients to use one of the first memory and the second memory based on a control signal, and a control logic configured to calculate a target capacity for data of a target client of the memory clients determined based on a layer configuration of an artificial neural network, and generate the control signal to store the data of the target client in the second memory based on a result of comparing the target capacity and the capacity of the second memory.Type: GrantFiled: July 15, 2021Date of Patent: March 11, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Woo Jang, Jinook Song, Sehwan Lee
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Patent number: 12241010Abstract: Disclosed are a perovskite color converter and a method for manufacturing the same. In order to maintain strong physical properties, the siloxane resin is synthesized in two steps. The silane precursor performs siloxane bond through a non-aqueous sol-gel reaction to form a siloxane resin, and a bond between methacrylate group, and a bond between methacrylate group and an organic ligand are formed through a secondary cross-linking reaction.Type: GrantFiled: November 5, 2021Date of Patent: March 4, 2025Assignees: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Tae-Woo Lee, Byeong-Soo Bae, Young-Hoon Kim, Jun-Ho Jang
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Publication number: 20250019135Abstract: A sealing structure may include a lid including a first lid face, a second lid face opposite to the first lid face, and a fragile area between the first lid face and the second lid face, a cover including a first cover face facing the second lid face and covering the fragile area and a second cover face opposite to the first cover face, wherein a first distance between the second lid face and the first cover face is substantially equal to or less than a second distance between the first cover face and the second cover face, and a connector configured to connect the lid and the cover.Type: ApplicationFiled: September 30, 2024Publication date: January 16, 2025Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wooram HONG, Hyun Do CHOI, Dal HEO, Youngchun KWON, Hyukju KWON, Gahee KIM, Bosung KIM, Jeonghun KIM, Jin Woo KM, Min Sik PARK, Youngjin PARK, Hyungtae SEO, Won Seok OH, Dongseon LEE, Sangyoon LEE, Jaejun CHANG, Jun Won JANG, Hyunjeong JEON, Joon-Kee CHO, Byung-Kwon CHOI, Won Je CHOI, Younsuk CHOI, Taesin HA
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Publication number: 20240411599Abstract: An integrated circuit includes: a central processing unit (CPU) core; an accelerator; and an acceleration instruction queue connected to the CPU core and the accelerator. The CPU core is to: fetch and decode one or more instructions from among an instruction sequence in a programmed order; determine an instruction from among the one or more instructions containing an acceleration workload encoded therein; and queue the instruction containing the acceleration workload encoded therein in the acceleration instruction queue.Type: ApplicationFiled: July 21, 2023Publication date: December 12, 2024Inventors: Zhi-Gang Liu, Jun Woo Jang, Sehwan Lee, Dongkyun Kim
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Patent number: 12099912Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: GrantFiled: June 19, 2019Date of Patent: September 24, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Patent number: 12086700Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: GrantFiled: August 27, 2019Date of Patent: September 10, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Patent number: 12073302Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: GrantFiled: July 10, 2023Date of Patent: August 27, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Publication number: 20240256828Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: ApplicationFiled: March 11, 2024Publication date: August 1, 2024Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Publication number: 20240232091Abstract: A computing method and device with data sharing re provided. The method includes loading, by a loader, input data of an input feature map stored in a memory in loading units according to a loading order, storing, by a buffer controller, the loaded input data in a reuse buffer of an address rotationally allocated according to the loading order, and transmitting, by each of a plurality of senders, to an executer respective input data corresponding to each output data of respective convolution operations among the input data stored in the reuse buffer, wherein portions of the transmitted respective input data overlap other.Type: ApplicationFiled: March 27, 2024Publication date: July 11, 2024Applicant: Samsung Electronics Co., LtdInventors: Yoojin KIM, Channoh KIM, Hyun Sun PARK, Sehwan LEE, Jun-Woo JANG
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Patent number: 11971823Abstract: A computing method and device with data sharing are provided. The method includes loading, by a loader, input data of an input feature map stored in a memory in loading units according to a loading order, storing, by a buffer controller, the loaded input data in a reuse buffer of an address rotationally allocated according to the loading order, and transmitting, by each of a plurality of senders, to an executer respective input data corresponding to each output data of respective convolution operations among the input data stored in the reuse buffer, wherein portions of the transmitted respective input data overlap other.Type: GrantFiled: May 11, 2021Date of Patent: April 30, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yoojin Kim, Channoh Kim, Hyun Sun Park, Sehwan Lee, Jun-Woo Jang
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Patent number: 11954574Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: GrantFiled: June 19, 2019Date of Patent: April 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Publication number: 20240013029Abstract: A method and apparatus for multi-task processing are disclosed. The method includes obtaining a base output corresponding to a first layer, restoring an input map corresponding to a second layer, obtaining an output map corresponding to the second layer, obtaining a delta output map corresponding to the second layer, and storing the base output map and the delta output map.Type: ApplicationFiled: June 19, 2023Publication date: January 11, 2024Inventors: JUN-WOO JANG, Jaekang Shin, Lee-Sup Kim
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Publication number: 20230351151Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Patent number: 11797461Abstract: A data transmission method for a convolution operation, and a convolution operation apparatus including a fetcher that includes a loader, at least one sender, a buffer controller, and a reuse buffer. The method includes loading, by the loader, input data of an input feature map according to a loading order, based on input data stored in the reuse buffer, a shape of a kernel to be used for a convolution operation, and two-dimensional (2D) zero-value information of weights of the kernel; storing, by the buffer controller, the loaded input data in the reuse buffer of an address cyclically assigned according to the loading order; and selecting, by each of the at least one sender, input data corresponding to each output data of a convolution operation among the input data stored in the reuse buffer, based on one-dimensional (1D) zero-value information of the weights, and outputting the selected input data.Type: GrantFiled: July 6, 2022Date of Patent: October 24, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hyunsun Park, Jun-Woo Jang, Yoojin Kim, Channoh Kim
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Publication number: 20230325462Abstract: A processor-implemented apparatus includes a forward transform module configured to transform input feature maps (IFMs) by performing a forward transform operation in a Winograd convolution (WinConv) domain, multiply and accumulate array (MAA) units configured to multiply the transformed IFMs by transformed kernels and perform a first inverse transform operation based on results of the multiplying, and an inverse transform module configured to generate output feature maps (OFMs) based on a result of the first inverse transform operation.Type: ApplicationFiled: April 5, 2023Publication date: October 12, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gopinath Vasanth MAHALE, Pramod Parameshwara UDUPA, Jun-Woo JANG, Kiran Kolar CHANDRASEKHARAN, Sehwan LEE
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Patent number: 11783161Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: GrantFiled: June 19, 2019Date of Patent: October 10, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Patent number: 11783162Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: GrantFiled: August 27, 2019Date of Patent: October 10, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Patent number: 11775802Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: GrantFiled: August 27, 2019Date of Patent: October 3, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Patent number: 11775801Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.Type: GrantFiled: August 27, 2019Date of Patent: October 3, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph H. Hassoun, Lei Wang, Sehwan Lee, JoonHo Song, Jun-Woo Jang, Yibing Michelle Wang, Yuecheng Li
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Patent number: 11736803Abstract: Disclosed herein is a full-screen display device capable of sufficiently securing light transmittance of a sensor area overlapping a sensor unit in a pixel array and minimizing deterioration in perceived image quality of the sensor area. The pixels are arranged in the sensor area overlapping the sensor unit in the pixel array of the full-screen display device such that the number of pixels gradually decreases from the outer periphery toward the center of the sensor area in units of masks, and the area of a transmission portion gradually increases from the outer periphery toward the center of the sensor area in units of masks.Type: GrantFiled: June 22, 2022Date of Patent: August 22, 2023Assignee: LG Display Co., Ltd.Inventors: Young-Tae Kim, Jun-Woo Jang, Tae-Yong Park, Woong-Jin Seo