Patents by Inventor Junya Ishii

Junya Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9559063
    Abstract: A semiconductor device includes an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: January 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Watanabe, Junya Ishii, Hirofumi Saitou, Hiroyasu Kitajima, Tatsuki Kojima, Yoshitsugu Kawashima
  • Publication number: 20140027928
    Abstract: A semiconductor device an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 30, 2014
    Inventors: Takeshi WATANABE, Junya ISHII, Hirofumi SAITOU, Hiroyasu KITAJIMA, Tatsuki KOJIMA, Yoshitsugu KAWASHIMA
  • Patent number: 8580148
    Abstract: It is an object of the present invention to provide an alkaline earth metal aluminate phosphor having good heat resistance and durability against vacuum ultraviolet rays and ultraviolet rays, among others, and a method of producing the same. An alkaline earth metal aluminate phosphor containing bivalent europium as an activator, which contains at least one element (e) selected from the group consisting of indium, tungsten, niobium, bismuth, molybdenum, tantalum, thallium and lead.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: November 12, 2013
    Assignee: Sakai Chemical Industry Co., Ltd.
    Inventors: Seiko Hirayama, Keita Kobayashi, Junya Ishii, Mizuho Wada, Shinji Nakahara
  • Publication number: 20060091360
    Abstract: It is an object of the present invention to provide an alkaline earth metal aluminate phosphor having good heat resistance and durability against vacuum ultraviolet rays and ultraviolet rays, among others, and a method of producing the same. An alkaline earth metal aluminate phosphor containing bivalent europium as an activator, which contains at least one element (e) selected from the group consisting of indium, tungsten, niobium, bismuth, molybdenum, tantalum, thallium and lead.
    Type: Application
    Filed: March 12, 2004
    Publication date: May 4, 2006
    Inventors: Seiko Hirayama, Keita Kobayashi, Junya Ishii
  • Patent number: 6815325
    Abstract: A test method for a semiconductor device in which a bonding pad thereof comprises a first interconnect layer and a second interconnect layer, the bonding pad comprising: a plurality of connection parts, provided within a plurality of slit-shaped trenches formed in an interlayer insulation film, respectively, and connecting the first interconnect layer and the second interconnect layer, the connection parts being disposed in one direction with a prescribed spacing, wherein the method comprising; contacting a test probe for testing the semiconductor device with the bonding pads so as to be in a direction parallel to a longitudinal direction of the connection part.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: November 9, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Junya Ishii
  • Publication number: 20040048402
    Abstract: A test method for a semiconductor device in which a bonding pad thereof comprises a first interconnect layer and a second interconnect layer, the bonding pad comprising: a plurality of connection parts, provided within a plurality of slit-shaped trenches formed in an interlayer insulation film, respectively, and connecting the first interconnect layer and the second interconnect layer, the connection parts being disposed in one direction with a prescribed spacing, wherein the method comprising; contacting a test probe for testing the semiconductor device with the bonding pads so as to be in a direction parallel to a longitudinal direction of the connection part.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 11, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Junya Ishii
  • Patent number: 6653729
    Abstract: A test method for a semiconductor device in which a bonding pad thereof comprises a first interconnect layer and a second interconnect layer, the bonding pad comprising: a plurality of connection parts, provided within a plurality of slit-shaped trenches formed in an interlayer insulation film, respectively, and connecting the first interconnect layer and the second interconnect layer, the connection parts being disposed in one direction with a prescribed spacing, wherein the method comprising; contacting a test probe for testing the semiconductor device with the bonding pads so as to be in a direction parallel to a longitudinal direction of the connection part.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: November 25, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Junya Ishii
  • Publication number: 20020039801
    Abstract: A test method for a semiconductor device in which a bonding pad thereof comprises a first interconnect layer and a second interconnect layer, the bonding pad comprising: a plurality of connection parts, provided within a plurality of slit-shaped trenches formed in an interlayer insulation film, respectively, and connecting the first interconnect layer and the second interconnect layer, the connection parts being disposed in one direction with a prescribed spacing, wherein the method comprising; contacting a test probe for testing the semiconductor device with the bonding pads so as to be in a direction parallel to a longitudinal direction of the connection part.
    Type: Application
    Filed: September 24, 2001
    Publication date: April 4, 2002
    Inventor: Junya Ishii
  • Patent number: 5461352
    Abstract: A bandpass filter for the transmission of signals within a predetermined frequency bandwidth having a center frequency, which provides for substantial attenuation of the harmonic components of the center frequency of the filter. The bandpass filter includes at least one resonator comprising a strip conductor and a ground conductor formed on the surface of a dielectric substrate. The strip conductor is capacitively coupled to the ground conductor so as to substantially transmit the harmonic components of the center frequency of the filter to ground.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: October 24, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasumasa Noguchi, Hideyuki Miyake, Junya Ishii, Yukihiro Takeda