Patents by Inventor Junya Kudoh

Junya Kudoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit for communication including analog-to-digital conversion circuit
    Patent number: 7286074
    Abstract: A semiconductor integrated circuit having a built-in A/D conversion circuit which enables, where the A/D conversion circuit is to be built into a semiconductor chip, the required capacitance of the stabilization capacitor to be connected to the output terminals of reference voltage generators for generating reference voltages to be reduced is to be provided to contribute to preventing the number of external terminals and the chip size from increasing.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: October 23, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Junya Kudoh, Kouichi Yahagi, Tatsuji Matsuura
  • Semiconductor integrated circuit for communication including analog-to-digital conversion circuit
    Publication number: 20060022861
    Abstract: A semiconductor integrated circuit having a built-in A/D conversion circuit which enables, where the A/D conversion circuit is to be built into a semiconductor chip, the required capacitance of the stabilization capacitor to be connected to the output terminals of reference voltage generators for generating reference voltages to be reduced is to be provided to contribute to preventing the number of external terminals and the chip size from increasing.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 2, 2006
    Inventors: Junya Kudoh, Kouichi Yahagi, Tatsuji Matsuura
  • Signal transmission method, signal transmission circuit and information processing system using same
    Patent number: 5483110
    Abstract: One paired wiring traveling in parallel to a transmission path of a signal and a transmission path of reference voltage is used, and a terminal end resistor matched with the characteristic impedance is installed, and in a receiving circuit connected thereto, a differential input circuit with offset set to about 1/2 of the terminal end voltage is used, and an output circuit of open drain is used in a transmitting circuit. A high-speed information processing section using such a bus circuit and a low-speed information processing section using a conventional low-speed bus are mutually connected through an interface circuit to construct the system hierarchically.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: January 9, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Koide, Masao Mizukami, Satoshi Hososaka, Junya Kudoh