Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floating electrodes and control electrodes are provided on the active region columns. An interlayer insulating film formed as a layer below an upper wiring is provided on the active region and the control electrodes. Conductive sections that electrically connect the upper wiring and the active region are respectively provided on the concave portions on the active region rows.

Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floating electrodes and control electrodes are provided on the active region columns. An interlayer insulating film formed as a layer below an upper wiring is provided on the active region and the control electrodes. Conductive sections that electrically connect the upper wiring and the active region are respectively provided on the concave portions on the active region rows.

Abstract: An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floating electrodes and control electrodes are provided on the active region columns. An interlayer insulating film formed as a layer below an upper wiring is provided on the active region and the control electrodes. Conductive sections that electrically connect the upper wiring and the active region are respectively provided on the concave portions on the active region rows.

Abstract: A semiconductor memory device includes: a laminated body which has a floating-gate-forming groove and includes a semiconductor support layer, an impurity diffusion layer, an ion-implantation-damage protection film, and an interlayer insulating film; a floating-gate-insulating film; a floating gate disposed on the floating-gate-insulating film so as to be buried in the floating-gate-forming groove; a control-gate-insulating film disposed on a surface area of the floating gate; and a control gate disposed on the control-gate-insulating film above the floating gate, wherein the floating-gate-insulating film contacts with the semiconductor support layer at the bottom of the floating-gate-forming groove, the floating-gate-insulating film contacts with the impurity diffusion layer, the ion-implantation-damage protection film, and the interlayer insulating film at the side wall of the floating-gate-forming groove.

Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: A semiconductor device includes a first insulating layer; a first poly-silicon plug formed in the first insulating layer; a second insulating layer, formed on the first insulating layer; and a second poly-silicon plug that is formed in the second insulating layer. At least one of the first and second insulating layers is made from non-doped silicate glass. The first and second poly-silicon plugs are electrically coupled to each other in a thickness direction. Preferably, both the first and second insulating layers are made from non-doped silicate glass.

Abstract: A semiconductor memory device includes: a laminated body which has a floating-gate-forming groove and includes a semiconductor support layer, an impurity diffusion layer, an ion-implantation-damage protection film, and an interlayer insulating film; a floating-gate-insulating film; a floating gate disposed on the floating-gate-insulating film so as to be buried in the floating-gate-forming groove; a control-gate-insulating film disposed on a surface area of the floating gate; and a control gate disposed on the control-gate-insulating film above the floating gate, wherein the floating-gate-insulating film contacts with the semiconductor support layer at the bottom of the floating-gate-forming groove, the floating-gate-insulating film contacts with the impurity diffusion layer, the ion-implantation-damage protection film, and the interlayer insulating film at the side wall of the floating-gate-forming groove.

Abstract: A semiconductor device includes a first insulating layer; a first poly-silicon plug formed in the first insulating layer; a second insulating layer, formed on the first insulating layer; and a second poly-silicon plug that is formed in the second insulating layer. At least one of the first and second insulating layers is made from non-doped silicate glass. The first and second poly-silicon plugs are electrically coupled to each other in a thickness direction. Preferably, both the first and second insulating layers are made from non-doped silicate glass.

Abstract: An active region (101) is provided which comprises a plurality of active region columns (52) extending in a first direction and a plurality of active region row (53) extending in a second direction substantially orthogonal to the first direction and having concave portions (105). Floating electrodes (103) and control electrodes (104) are provided on the active region columns (52). An interlayer insulting film (109) formed as a layer below an upper wiring (110) is provided on the active region (101) and the control electrodes (104). Conductive sections (106) that electrically connect the upper wiring (110) and the active region (101) are respectively provided on the concave portions (105) on the active region rows (53).