Patents by Inventor Junya Masumi

Junya Masumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interface circuit for use in a semiconductor integrated circuit
    Patent number: 5841619
    Abstract: To an input terminal is connected one end of the source-to-drain current path of an NMOS the gate of which is connected to Vcc. The other end of the current path of the NMOS is connected by a protection circuit comprised of a PMOS and an NMOS to the common gates of a PMOS and an NMOS in the input stage of an internal circuit. In the protection circuit, the PMOS has its source and gate connected to Vcc and its drain connected to the common gates of the PMOS and the NMOS, while the NMOS has its source and gate connected to Vss and its drain connected to the common drains of the PMOS and the NMOS.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: November 24, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Shigehara, Yasunori Tanaka, Junya Masumi