Patents by Inventor Junya Nagano

Junya Nagano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230310186
    Abstract: A stent formed by weaving a wire into a tubular shape includes intersecting portions at which the wire intersects and interlocking portions at which the wire interlocks. In the stent, at least two stretch assisting columns are continuously disposed in a circumferential direction of the stent, each of the at least two stretch assisting columns including a larger number of the intersecting portions than the interlocking portions in an axial direction of the stent, and at least one contraction assisting column including a larger number of the interlocking portions than the intersecting portions in the axial direction is disposed. When the stent is equally divided in the circumferential direction by a plane including an axis of the stent and a first equally-divided region includes the at least two stretch assisting columns continuously disposed, a second equally-divided region includes a majority of the interlocking portions.
    Type: Application
    Filed: January 26, 2023
    Publication date: October 5, 2023
    Inventors: Junya NAGANO, Haruki OKA
  • Patent number: 6960494
    Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: November 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
  • Publication number: 20050051810
    Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
    Type: Application
    Filed: October 21, 2004
    Publication date: March 10, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
  • Patent number: 6836012
    Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: December 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
  • Publication number: 20020140095
    Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
    Type: Application
    Filed: March 29, 2002
    Publication date: October 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
  • Patent number: 5715147
    Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: February 3, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junya Nagano
  • Patent number: 5646830
    Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: July 8, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junya Nagano
  • Patent number: 5613295
    Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: March 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junya Nagano
  • Patent number: 5552966
    Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: September 3, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junya Nagano
  • Patent number: 5473514
    Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: December 5, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junya Nagano