Patents by Inventor Junya Nagano
Junya Nagano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230310186Abstract: A stent formed by weaving a wire into a tubular shape includes intersecting portions at which the wire intersects and interlocking portions at which the wire interlocks. In the stent, at least two stretch assisting columns are continuously disposed in a circumferential direction of the stent, each of the at least two stretch assisting columns including a larger number of the intersecting portions than the interlocking portions in an axial direction of the stent, and at least one contraction assisting column including a larger number of the interlocking portions than the intersecting portions in the axial direction is disposed. When the stent is equally divided in the circumferential direction by a plane including an axis of the stent and a first equally-divided region includes the at least two stretch assisting columns continuously disposed, a second equally-divided region includes a majority of the interlocking portions.Type: ApplicationFiled: January 26, 2023Publication date: October 5, 2023Inventors: Junya NAGANO, Haruki OKA
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Patent number: 6960494Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: GrantFiled: October 21, 2004Date of Patent: November 1, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Publication number: 20050051810Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: ApplicationFiled: October 21, 2004Publication date: March 10, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Patent number: 6836012Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: GrantFiled: March 29, 2002Date of Patent: December 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Publication number: 20020140095Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: ApplicationFiled: March 29, 2002Publication date: October 3, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Patent number: 5715147Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.Type: GrantFiled: April 30, 1996Date of Patent: February 3, 1998Assignee: Kabushiki Kaisha ToshibaInventor: Junya Nagano
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Patent number: 5646830Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.Type: GrantFiled: June 2, 1995Date of Patent: July 8, 1997Assignee: Kabushiki Kaisha ToshibaInventor: Junya Nagano
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Patent number: 5613295Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.Type: GrantFiled: June 2, 1995Date of Patent: March 25, 1997Assignee: Kabushiki Kaisha ToshibaInventor: Junya Nagano
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Patent number: 5552966Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.Type: GrantFiled: June 2, 1995Date of Patent: September 3, 1996Assignee: Kabushiki Kaisha ToshibaInventor: Junya Nagano
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Patent number: 5473514Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.Type: GrantFiled: June 3, 1994Date of Patent: December 5, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Junya Nagano