Abstract: The DA converter according to the present invention includes: first and second analog segment units a plurality of capacitors of sampling capacitor groups charged according to signal levels of digital signals input in a sampling phase; and a calculation unit that outputs an analog signal according to a charged voltage of each capacitor of the sampling capacitor group of the first or second analog segment unit in an integral phase, wherein, when one analog segment unit of the first and second analog segment units is in the sampling phase, the other analog segment unit is in the integral phase.

Abstract: The DA converter according to the present invention includes: first and second analog segment units a plurality of capacitors of sampling capacitor groups charged according to signal levels of digital signals input in a sampling phase; and a calculation unit that outputs an analog signal according to a charged voltage of each capacitor of the sampling capacitor group of the first or second analog segment unit in an integral phase, wherein, when one analog segment unit of the first and second analog segment units is in the sampling phase, the other analog segment unit is in the integral phase.

Abstract: The present invention relates to a control method of a D/A converter, a D/A converter, a control method of an A/D converter, and an A/D converter that can suppress an existing n-th harmonic without using a large-scale circuit, such as a bootstrap. A D/A converter (10) of the present invention is a D/A converter (10) that can suppress the generation of an existing n-th harmonic (n is an integer of 2 or more) of an analog output signal. The D/A converter (10) includes a D/A conversion unit (11) that converts an input digital signal into an analog signal and a control unit (12) that arbitrarily controls the timing of the sampling phase and the integral phase of the D/A conversion unit (11). The D/A conversion unit (11) is configured to generate an arbitrary n-th harmonic and superimpose the arbitrary n-th harmonic on an analog output signal including the existing n-th harmonic.

Abstract: To provide a D/A converter including a sampling circuit capable of suppressing a high-frequency component in an input signal without obstructing downsizing of electronic equipment. A D/A converter includes a first capacitative element unit including plural sampling capacitors, a second capacitative element unit including plural sampling capacitors, a first switch unit including the plural switches configured to store charges in the plural sampling capacitors of the first capacitative element unit and to transfer the charge, and a second switch unit including the plural switches configured to store charges in the plural sampling capacitors of the second capacitative element unit and to transfer the charge. The first and the second switch units operate alternately.

Abstract: To provide a D/A converter including a sampling circuit capable of suppressing a high-frequency component in an input signal without obstructing downsizing of electronic equipment. A D/A converter includes a first capacitative element unit including plural sampling capacitors, a second capacitative element unit including plural sampling capacitors, a first switch unit including the plural switches configured to store charges in the plural sampling capacitors of the first capacitative element unit and to transfer the charge, and a second switch unit including the plural switches configured to store charges in the plural sampling capacitors of the second capacitative element unit and to transfer the charge. The first and the second switch units operate alternately.

Abstract: The present invention relates to a control method of a D/A converter, a D/A converter, a control method of an A/D converter, and an A/D converter that can suppress an existing n-th harmonic without using a large-scale circuit, such as a bootstrap. A D/A converter (10) of the present invention is a D/A converter (10) that can suppress the generation of an existing n-th harmonic (n is an integer of 2 or more) of an analog output signal. The D/A converter (10) includes a D/A conversion unit (11) that converts an input digital signal into an analog signal and a control unit (12) that arbitrarily controls the timing of the sampling phase and the integral phase of the D/A conversion unit (11). The D/A conversion unit (11) is configured to generate an arbitrary n-th harmonic and superimpose the arbitrary n-th harmonic on an analog output signal including the existing n-th harmonic.

Abstract: The successive approximation A/D converter includes: switch groups 105—1 to 105—x each of which is connected to the other end of each corresponding capacitor of capacitors 106—1 to 106—x to selectively switch a capacitor to be applied to a successive comparison in response to a switch group control signal Ct1; a comparator 104 for making a successive comparison of a comparison voltage VSN based on a holding voltage on each corresponding capacitor, selected through the switch groups from among the capacitors, with a predetermined reference voltage VC in synchronization with a timing control signal CLK to obtain a judgment output according to the comparison result; and a voltage application part 107 for applying a predetermined voltage to the comparison voltage based on a form-of-voltage application control signal Ct2 for a predetermined period when a predetermined time has elapsed after the successive comparison.

Abstract: An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.

Abstract: A digital-analog converter circuit includes sampling capacitive elements (111, 112, . . . , 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, . . . , DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, . . . , 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, . . . , 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract: The successive approximation A/D converter includes: switch groups 105—1 to 105—x each of which is connected to the other end of each corresponding capacitor of capacitors 106—1 to 106—x to selectively switch a capacitor to be applied to a successive comparison in response to a switch group control signal Ct1; a comparator 104 for making a successive comparison of a comparison voltage VSN based on a holding voltage on each corresponding capacitor, selected through the switch groups from among the capacitors, with a predetermined reference voltage VC in synchronization with a timing control signal CLK to obtain a judgment output according to the comparison result; and a voltage application part 107 for applying a predetermined voltage to the comparison voltage based on a form-of-voltage application control signal Ct2 for a predetermined period when a predetermined time has elapsed after the successive comparison.

Abstract: A digital-analog converter circuit includes sampling capacitive elements (111, 112, . . . , 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, . . . , DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, . . . , 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, . . . , 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract: An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.