Patents by Inventor Junya Nishii

Junya Nishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879349
    Abstract: A method for manufacturing a semiconductor device having a edge termination region comprises a stacking process, an ion implantation process, and a heat treatment process. In the stacking process, a p-type semiconductor layer containing a p-type impurity is stacked on an n-type semiconductor layer containing an n-type impurity. In the ion implantation process, at least one of the n-type impurity and the p-type impurity is ion-implanted into the p-type semiconductor layer located in the edge termination region. The ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a p-type impurity containing region in at least part of the n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 29, 2020
    Assignee: TOYODA GOSET CO., LTD.
    Inventors: Tohru Oka, Nariaki Tanaka, Junya Nishii
  • Patent number: 10854454
    Abstract: To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 1, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yukihisa Ueno, Nariaki Tanaka, Junya Nishii, Toru Oka
  • Publication number: 20200287008
    Abstract: The present invention provides a Group III nitride semiconductor device in which current concentration at the corners of the trench is suppressed. The semiconductor device has a pattern in which regular hexagonal unit cells are arranged in a honeycomb pattern. The semiconductor layer is sectionalized into regular hexagonal patterns by the trench. The recess has a small regular hexagonal pattern contained in the regular hexagonal pattern of the semiconductor layer sectionalized by the trench, which is obtained by reducing the regular hexagon of the semiconductor layer with the same center. Moreover, the regular hexagonal pattern of the recess is rotated by 30° with respect to the regular hexagon of the semiconductor layer. The Mg activation ratio is lower in the vicinity of corners of the trench than that in other regions in the vicinity of side walls of the trench of the p-type layer.
    Type: Application
    Filed: February 19, 2020
    Publication date: September 10, 2020
    Inventors: Junya Nishii, Yuh Kimura
  • Patent number: 10490408
    Abstract: A method for manufacturing a semiconductor device comprises: a stacking process that stacks a p-type semiconductor layer of Group III nitride containing a p-type impurity on a first n-type semiconductor layer of Group III nitride containing an n-type impurity; a p-type ion implantation process that ion-implants the p-type impurity into the p-type semiconductor layer; and a heat treatment process that performs heat treatment to activate the ion-implanted p-type impurity. The p-type ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a first p-type impurity containing region in at least part of the first n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: November 26, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Junya Nishii, Tohru Oka, Nariaki Tanaka
  • Publication number: 20190341260
    Abstract: To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region.
    Type: Application
    Filed: April 22, 2019
    Publication date: November 7, 2019
    Inventors: Yukihisa UENO, Nariaki TANAKA, Junya NISHII, Toru OKA
  • Publication number: 20190103464
    Abstract: A semiconductor device comprises: a nitride semiconductor layer; an oxide insulating film formed to contact the nitride semiconductor layer; and a gate electrode formed to contact the oxide insulating film and made of metal nitride in a crystal orientation including at least one of the (200) orientation and the (220) orientation.
    Type: Application
    Filed: September 19, 2018
    Publication date: April 4, 2019
    Inventors: Takatomi Izumi, Junya Nishii, Yuhei Ikemoto
  • Patent number: 10236373
    Abstract: To suppress current leakage in a semiconductor device having a gate insulating film and a gate electrode. A gate electrode is continuously formed in a film via a gate insulating film on the bottom surface of a trench, the side surfaces of a trench, and the top surfaces of a second n-type layer in the vicinity of the side surfaces of the trench. The ends of the bottom surface of the gate electrode are aligned with the ends of the top surface of the gate insulating film, and the ends of the bottom surface of the gate insulating film are formed in contact with the surfaces of the second n-type layer facing the ends of the bottom surface of the gate electrode. The passivation film covers the entire top surface of the device except the contact holes of the gate electrode and the source electrode.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: March 19, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Junichiro Kurosaki, Tohru Oka, Junya Nishii, Tsutomu Ina
  • Patent number: 10193525
    Abstract: An SAW device (1) has a piezoelectric substrate (3) propagating acoustic waves, and a comb-shaped electrode (6) arranged on a first surface (3a) of the piezoelectric substrate (3). The SAW device (1) has a columnar terminal (15) located on the first surface (3a) and electrically connected to the comb-shaped electrode (6), and a cover member (9) covering the a side surface of the terminal (15). The terminal (15) comprises, in a first region in the height direction of height thereof, a larger diameter on the side of the first surface (3a) compared with the diameter on the side opposite to the first surface (3a).
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: January 29, 2019
    Assignee: KYOCERA Corporation
    Inventors: Toru Fukano, Junya Nishii
  • Publication number: 20180286945
    Abstract: A method for manufacturing a semiconductor device having a edge termination region comprises a stacking process, an ion implantation process, and a heat treatment process. In the stacking process, a p-type semiconductor layer containing a p-type impurity is stacked on an n-type semiconductor layer containing an n-type impurity. In the ion implantation process, at least one of the n-type impurity and the p-type impurity is ion-implanted into the p-type semiconductor layer located in the edge termination region. The ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a p-type impurity containing region in at least part of the n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.
    Type: Application
    Filed: March 13, 2018
    Publication date: October 4, 2018
    Inventors: Tohru Oka, Nariaki Tanaka, Junya Nishii
  • Publication number: 20180286685
    Abstract: A method for manufacturing a semiconductor device comprises: a stacking process that stacks a p-type semiconductor layer of Group III nitride containing a p-type impurity on a first n-type semiconductor layer of Group III nitride containing an n-type impurity; a p-type ion implantation process that ion-implants the p-type impurity into the p-type semiconductor layer; and a heat treatment process that performs heat treatment to activate the ion-implanted p-type impurity. The p-type ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a first p-type impurity containing region in at least part of the first n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.
    Type: Application
    Filed: March 8, 2018
    Publication date: October 4, 2018
    Inventors: Junya NISHII, Tohru OKA, Nariaki TANAKA
  • Patent number: 10050600
    Abstract: A SAW device (1) comprises a substrate (3); SAW elements (10) on a first main surface (3a) of the substrate (3); first lines (intermediate lines (29) and output side lines (31)) that are disposed upon the first main face (3a) and connected to the SAW elements (10); an insulator (21) that is layered upon the first lines; second lines (a second ground line (33b) and a third ground line (33c)) that are layered upon the insulator (21) and configure three-dimensional wiring parts (39) with the first lines; and a cover (5) that seals the SAW elements (10) and the three-dimensional wiring parts (39). Wiring spaces (53), formed between the first main face (3a) and the cover (5), houses the three-dimensional wiring parts (39), without housing the SAW elements (10).
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: August 14, 2018
    Assignee: KYOCERA Corporation
    Inventors: Hiroaki Ochiai, Junya Nishii, Tsuyoshi Nakai
  • Patent number: 9991345
    Abstract: There is provided a semiconductor device comprising a group III nitride semiconductor layer; a gate insulating film formed on the group III nitride semiconductor layer; and a gate electrode formed on the gate insulating film. The gate insulating film comprises a first film that is placed on the group III nitride semiconductor layer, includes silicon and has a higher crystallization temperature than a crystallization temperature of aluminum oxide; and a second film that is placed on the first film and contains aluminum oxide. The first film has a hydrogen concentration of not lower than 1×1021 atoms/cm3, a nitrogen concentration of not lower than 1×1019 atoms/cm3 and a carbon concentration of not lower than 1×1019 atoms/cm3. This configuration prevents crystallization of aluminum oxide.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: June 5, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tomoyuki Suzuki, Junya Nishii
  • Patent number: 9966447
    Abstract: A technique of manufacturing a semiconductor device of stable operation is provided. There is provided a method of manufacturing a semiconductor device comprising a first process of forming an insulating film from a nitrogen-containing organic metal used as raw material, on a semiconductor layer by atomic layer deposition; a second process of processing the insulating film by oxygen plasma treatment in an atmosphere including at least one of oxygen and ozone; and a third process of processing the insulating film by heat treatment in a nitrogen-containing atmosphere, after the second process.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: May 8, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Junya Nishii
  • Publication number: 20180097071
    Abstract: There is provided a semiconductor device comprising a group III nitride semiconductor layer; a gate insulating film formed on the group III nitride semiconductor layer; and a gate electrode formed on the gate insulating film. The gate insulating film comprises a first film that is placed on the group III nitride semiconductor layer, includes silicon and has a higher crystallization temperature than a crystallization temperature of aluminum oxide; and a second film that is placed on the first film and contains aluminum oxide. The first film has a hydrogen concentration of not lower than 1×1021 atoms/cm3, a nitrogen concentration of not lower than 1×1019 atoms/cm3 and a carbon concentration of not lower than 1×1019 atoms/cm3. This configuration prevents crystallization of aluminum oxide.
    Type: Application
    Filed: September 20, 2017
    Publication date: April 5, 2018
    Inventors: Tomoyuki SUZUKI, Junya NISHII
  • Publication number: 20170278935
    Abstract: A technique of manufacturing a semiconductor device of stable operation is provided. There is provided a method of manufacturing a semiconductor device comprising a first process of forming an insulating film from a nitrogen-containing organic metal used as raw material, on a semiconductor layer by atomic layer deposition; a second process of processing the insulating film by oxygen plasma treatment in an atmosphere including at least one of oxygen and ozone; and a third process of processing the insulating film by heat treatment in a nitrogen-containing atmosphere, after the second process.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 28, 2017
    Inventor: Junya Nishii
  • Patent number: 9548204
    Abstract: There is provided a semiconductor device comprising a semiconductor layer that is made of a gallium-containing group III-V compound; and a first insulating film that is in contact with the semiconductor layer and contains silicon. An average density of gallium in the first insulating film between an interface of the first insulating film and the semiconductor layer and a plane away from the interface by 30 nm is less than 1.0×1018 cm?3. This configuration suppresses a decrease in flat band voltage and a decrease in threshold voltage.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: January 17, 2017
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Junya Nishii, Tohru Oka
  • Patent number: 9503049
    Abstract: A SAW element has a substrate; an IDT electrode located on an upper surface of the substrate and comprises Al or an alloy containing Al; a first film located on an upper surface of the IDT electrode; and a protective layer which covers the IDT electrode provided with the first film and the portion of the substrate exposed from the IDT electrode, which has a thickness from the upper surface of the substrate larger than a total thickness of the IDT electrode and first film, and which contains a silicon oxide. The first film contains a material which has a larger acoustic impedance than the material (Al or the alloy containing Al) of the IDT electrode and the silicon oxide and which has a slower propagation velocity of an acoustic wave than the material of the IDT electrode and the silicon oxide.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 22, 2016
    Assignee: KYOCERA CORPORATION
    Inventors: Junya Nishii, Tetsuya Kishino, Hiroyuki Tanaka, Kyohei Kobayashi, Kenji Yamamoto, Masahisa Shimozono, Takanori Ikuta, Michiaki Nishimura
  • Publication number: 20160329878
    Abstract: A SAW device (1) comprises a substrate (3); SAW elements (10) on a first main surface (3a) of the substrate (3); first lines (intermediate lines (29) and output side lines (31)) that are disposed upon the first main face (3a) and connected to the SAW elements (10); an insulator (21) that is layered upon the first lines; second lines (a second ground line (33b) and a third ground line (33c)) that are layered upon the insulator (21) and configure three-dimensional wiring parts (39) with the first lines; and a cover (5) that seals the SAW elements (10) and the three-dimensional wiring parts (39). Wiring spaces (53), formed between the first main face (3a) and the cover (5), houses the three-dimensional wiring parts (39), without housing the SAW elements (10).
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventors: Hiroaki OCHIAI, Junya NISHII, Tsuyoshi NAKAI
  • Patent number: 9397633
    Abstract: A SAW device (1) comprises a substrate (3); SAW elements (10) on a first main surface (3a) of the substrate (3); first lines (intermediate lines (29) and output side lines (31)) that are disposed upon the first main face (3a) and connected to the SAW elements (10); an insulator (21) that is layered upon the first lines; second lines (a second ground line (33b) and a third ground line (33c)) that are layered upon the insulator (21) and configure three-dimensional wiring parts (39) with the first lines; and a cover (5) that seals the SAW elements (10) and the three-dimensional wiring parts (39). Wiring spaces (53), formed between the first main face (3a) and the cover (5), houses the three-dimensional wiring parts (39), without housing the SAW elements (10).
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: July 19, 2016
    Assignee: KYOCERA Corporation
    Inventors: Hiroaki Ochiai, Junya Nishii, Tsuyoshi Nakai
  • Patent number: 9299567
    Abstract: A manufacturing method of MIS (Metal Insulator Semiconductor)-type semiconductor device includes the steps of: forming a zirconium oxynitride (ZrON) layer; forming an electrode layer containing titanium nitride (TiN) on the zirconium oxynitride (ZrON) layer; and heating the electrode layer.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 29, 2016
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Kiyotaka Mizukami, Takahiro Sonoyama, Toru Oka, Junya Nishii