Patents by Inventor Junya Sagara

Junya Sagara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374178
    Abstract: Provided is a thermally activated delayed fluorescence-emitting organic EL element having a low driving voltage, high luminous efficiency, and a prolonged lifespan. The organic EL element contains one or more light-emitting layers between an anode and a cathode that face each other, and at least one light-emitting layer contains a host material composed of a carbazole compound represented by formula (1) and a thermally activated delayed fluorescence material composed of an indolocarbazole compound containing an indolocarbazole ring in its molecule. Here, L1 represents an aromatic group, and at least one R1 represents a carbazolyl group, and n is 1 or 2.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 28, 2022
    Assignee: NIPPON STEEL CHEMICAL & MATERIAL CO., LTD.
    Inventors: Yuta Sagara, Masashi Tada, Kazuaki Yoshimura, Junya Ogawa, Katsuhide Noguchi
  • Patent number: 8294282
    Abstract: The present invention provides a semiconductor device which comprises a substrate, a first semiconductor chip on a substrate, a second semiconductor chip on the first semiconductor chip, and an adhesive sheet between the first and second semiconductor chips. The second semiconductor chip has a mirrored back surface, and the adhesive sheet contains a metal impurity ion trapping agent.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidekazu Hayashi, Hiroshi Tomita, Junya Sagara, Shinya Takyu, Norihiro Togasaki, Tetsuya Kurosawa, Yukiko Kitajima
  • Patent number: 8231046
    Abstract: A wire bonding method involves bonding a wire in order at a first bonding point and a second bonding point; raising a capillary, through which the wire is inserted, on the second bonding point; cutting the wire by closing a clamper provided above the capillary at a time when the capillary has reached a prescribed height; and measuring a load incurred on the wire at a time of cutting of the wire.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Nakao, Junya Sagara, Katsuhiro Ishida, Noboru Okane
  • Publication number: 20110163459
    Abstract: A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
    Type: Application
    Filed: March 18, 2011
    Publication date: July 7, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junya Sagara, Shinya Takyu, Tetsuya Kurosawa
  • Patent number: 7932162
    Abstract: A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: April 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junya Sagara, Shinya Takyu, Tetsuya Kurosawa
  • Publication number: 20110068480
    Abstract: The present invention provides a semiconductor device which comprises a substrate, a first semiconductor chip on a substrate, a second semiconductor chip on the first semiconductor chip, and an adhesive sheet between the first and second semiconductor chips. The second semiconductor chip has a mirrored back surface, and the adhesive sheet contains a metal impurity ion trapping agent.
    Type: Application
    Filed: March 23, 2010
    Publication date: March 24, 2011
    Inventors: Hidekazu Hayashi, Hiroshi Tomita, Junya Sagara, Shinya Takyu, Norihiro Togasaki, Tetsuya Kurosawa, Yukiko Kitajima
  • Patent number: 7892890
    Abstract: Chips are stacked and mounted on a circuit board having external connection electrodes and mounted thereon by wire bonding. At least one of the chips stacked on the chip includes overhung portions each of which has a start point inside bonding pads, is made thinner in a direction towards the outer periphery to an end point reaching the side wall and forms a space used to accommodate ball bonding portions between the overhung portion and the main surface of the chip arranged in the lower stage on a backside corresponding in position to the bonding pads, and insulating members formed to cover the overhung portions and prevent bonding wires of the chip arranged in the lower stage from being brought into contact with the upper-stage chip.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: February 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kurosawa, Junya Sagara
  • Patent number: 7849897
    Abstract: An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: December 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mitsuhiro Nakao, Junya Sagara, Masayuki Dohi, Tatsuhiko Shirakawa
  • Publication number: 20100311224
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes forming a plurality of first trenches in a semiconductor substrate, forming an insulating member in the first trenches, removing a part of a portion of the insulating member, forming second trenches in the insulating member, and attaching a protection film. The semiconductor substrate has a first and a second main surface. The insulating member has an upper face located higher than the first main surface. The portion is located higher than the first main surface.
    Type: Application
    Filed: May 18, 2010
    Publication date: December 9, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Kurosawa, Junya Sagara, Shinya Takyu, Norihiro Togasaki
  • Publication number: 20100181367
    Abstract: A wire bonding method involves bonding a wire in order at a first bonding point and a second bonding point; raising a capillary, through which the wire is inserted, on the second bonding point; cutting the wire by closing a clamper provided above the capillary at a time when the capillary has reached a prescribed height; and measuring a load incurred on the wire at a time of cutting of the wire
    Type: Application
    Filed: September 22, 2009
    Publication date: July 22, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuhiro Nakao, Junya Sagara, Katsuhiro Ishida, Noboru Okane
  • Publication number: 20100112755
    Abstract: Chips are stacked and mounted on a circuit board having external connection electrodes and mounted thereon by wire bonding. At least one of the chips stacked on the chip includes overhung portions each of which has a start point inside bonding pads, is made thinner in a direction towards the outer periphery to an end point reaching the side wall and forms a space used to accommodate ball bonding portions between the overhung portion and the main surface of the chip arranged in the lower stage on a backside corresponding in position to the bonding pads, and insulating members formed to cover the overhung portions and prevent bonding wires of the chip arranged in the lower stage from being brought into contact with the upper-stage chip.
    Type: Application
    Filed: January 12, 2010
    Publication date: May 6, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kurosawa, Junya Sagara
  • Patent number: 7675153
    Abstract: Chips are stacked and mounted on a circuit board having external connection electrodes and mounted thereon by wire bonding. At least one of the chips stacked on the chip includes overhung portions each of which has a start point inside bonding pads, is made thinner in a direction towards the outer periphery to an end point reaching the side wall and forms a space used to accommodate ball bonding portions between the overhung portion and the main surface of the chip arranged in the lower stage on a backside corresponding in position to the bonding pads, and insulating members formed to cover the overhung portions and prevent bonding wires of the chip arranged in the lower stage from being brought into contact with the upper-stage chip.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: March 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kurosawa, Junya Sagara
  • Patent number: 7569921
    Abstract: A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: August 4, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Ohnishi
  • Publication number: 20090096110
    Abstract: A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junya SAGARA, Shinya TAKYU, Tetsuya KUROSAWA
  • Publication number: 20080110546
    Abstract: An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
    Type: Application
    Filed: August 24, 2007
    Publication date: May 15, 2008
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mitsuhiro Nakao, Junya Sagara, Masayuki Dohi, Tatsuhiko Shirakawa
  • Publication number: 20080099532
    Abstract: A wire bonding apparatus comprising: a capillary configured to have inserted therethrough a wire; a damper provided above the capillary and able to clamp hold the wire; and a load sensor configured to measure load incurred on the wire.
    Type: Application
    Filed: October 4, 2007
    Publication date: May 1, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuhiro Nakao, Junya Sagara, Katsuhiro Ishida, Noboru Okane
  • Publication number: 20070023875
    Abstract: A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second adhesive layer is filled between the first semiconductor element and the second semiconductor element. An element-side end portion of a first bonding wire connected to the first semiconductor element is buried in the insulating resin layer.
    Type: Application
    Filed: July 21, 2006
    Publication date: February 1, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Oonishi, Atsushi Yoshimura
  • Publication number: 20070023922
    Abstract: A semiconductor package includes a circuit board having connection pads formed on a front and back surfaces, and a wiring network connected to these connection pads, as a package base. Metal bumps connected to at least part of the connection pads on the front and back surfaces via the wiring network are formed on the back surface of the circuit board as external connection terminals. One or a plurality of semiconductor elements electrically connected to the connection pad on the front surface side is or are mounted on a first element mounting part provided on the front surface side of the circuit board. One or plurality of semiconductor elements electrically connected to the connection pad on the back surface side is or are mounted on a second element mounting part provided on the back surface side of the circuit board.
    Type: Application
    Filed: July 21, 2006
    Publication date: February 1, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Oonishi
  • Publication number: 20060232288
    Abstract: A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 19, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Ohnishi
  • Publication number: 20060175697
    Abstract: Chips are stacked and mounted on a circuit board having external connection electrodes and mounted thereon by wire bonding. At least one of the chips stacked on the chip includes overhung portions each of which has a start point inside bonding pads, is made thinner in a direction towards the outer periphery to an end point reaching the side wall and forms a space used to accommodate ball bonding portions between the overhung portion and the main surface of the chip arranged in the lower stage on a backside corresponding in position to the bonding pads, and insulating members formed to cover the overhung portions and prevent bonding wires of the chip arranged in the lower stage from being brought into contact with the upper-stage chip.
    Type: Application
    Filed: February 1, 2006
    Publication date: August 10, 2006
    Inventors: Tetsuya Kurosawa, Junya Sagara