Patents by Inventor Junya Shimada

Junya Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220190069
    Abstract: A display device includes an active matrix substrate; a light-emitting element layer including a plurality of first electrodes, a function layer, and a second electrode; and a sealing layer. The light-emitting element layer further includes an edge cover layer configured to cover an end portion of each one of the plurality of first electrodes. The edge cover layer includes a plurality of openings configured to expose the plurality of first electrodes included in a plurality of pixels. The plurality of openings include a first opening with a rectangular shape. A first individual vapor deposition film with a rectangular shape is formed on the first electrode covering the first opening. In the first individual vapor deposition film, projection portions projecting from sections corresponding to at least some opposing vertices of the first opening to an opposite side to the first opening are provided on the edge cover layer.
    Type: Application
    Filed: March 27, 2019
    Publication date: June 16, 2022
    Inventors: EIJI KOIKE, TOHRU SONODA, MASAHIRO INUZUKA, JUNYA SHIMADA
  • Patent number: 9293594
    Abstract: A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: March 22, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Jun Nishimura, Hideki Kitagawa, Atsuhito Murai, Hajime Imai, Shinya Tanaka, Mitsunori Imade, Tetsuo Kikuchi, Junya Shimada, Kazunori Morimoto
  • Patent number: 9111810
    Abstract: A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: August 18, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hideki Kitagawa, Shinya Tanaka, Hajime Imai, Atsuhito Murai, Mitsunori Imade, Tetsuo Kikuchi, Kazunori Morimoto, Junya Shimada, Jun Nishimura
  • Patent number: 9029861
    Abstract: Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: May 12, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Kikuchi, Yoshiharu Kataoka, Shinya Tanaka, Junya Shimada, Chikao Yamasaki
  • Publication number: 20140306225
    Abstract: Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes.
    Type: Application
    Filed: May 20, 2011
    Publication date: October 16, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Kikuchi, Yoshiharu Kataoka, Shinya Tanaka, Junya Shimada, Chikao Yamasaki
  • Patent number: 8786582
    Abstract: The present invention is to provide a display panel and a display apparatus which can reduce the picture-frame area while sufficiently preventing the delay of signals by allowing a required amount of current to flow. The display panel of the present invention is a display panel which includes a circuit substrate, and an opposed substrate facing the circuit substrate, and which is featured in that the circuit section is arranged in the picture-frame area of the display panel, in that the circuit section includes trunk wiring, and branch wiring connected to the gate electrode or the source electrode of a transistor in the circuit section, and in that all or a part of the trunk wiring is provided on the opposed substrate, and the branch wiring is provided on the circuit substrate so as to be electrically connected to the trunk wiring via a conductor.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: July 22, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Junya Shimada, Shinya Tanaka, Tetsuo Kikuchi, Chikao Yamasaki
  • Publication number: 20140197412
    Abstract: A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.
    Type: Application
    Filed: March 17, 2014
    Publication date: July 17, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Jun NISHIMURA, Hideki KITAGAWA, Atsuhito MURAI, Hajime IMAI, Shinya TANAKA, Mitsunori IMADE, Tetsuo KIKUCHI, Junya SHIMADA, Kazunori MORIMOTO
  • Patent number: 8781059
    Abstract: A shift register is formed by connecting unit circuits 11 in multi-stage. One electrode of a capacitor Cap2 in the unit circuit 11 is connected to the gate terminal (node N1) of a transistor T2, and the other connected to a node N2. A compensation circuit composed of transistors T3 to T5 provides a clock signal CKB to the node N2 when the node N1 potential is at low level, and applies a low-level potential to the node N2 when the node N1 potential is at high level. Accordingly, even when the gate potential of the transistor T2 changes with a change in a clock signal CK, a signal that cancels out the change is provided through the capacitor Cap2, stabilizing the gate potential of the transistor T2. Thus, a change in the control terminal potential of an output transistor associated with a change in a clock signal is prevented.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: July 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Kikuchi, Shinya Tanaka, Junya Shimada, Chikao Yamasaki
  • Patent number: 8742424
    Abstract: The present invention provides a shift register and a display device, each of which operates stably. The present invention relate to a shift register, comprising a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, the thin-film transistor being a bottom gate thin-film transistor which includes a comb-shaped source/drain structure, the gate electrode being provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: June 3, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Chikao Yamasaki, Tetsuo Kikuchi, Shinya Tanaka, Junya Shimada
  • Patent number: 8723845
    Abstract: A signal distribution circuit (3) includes (i) a redundancy TFT element (8) provided so as to have a channel width identical to those of driving TFT elements (7), (ii) first redundancy lines (9a, 9b), (iii) a second redundancy line (10), and (iv) a third redundancy line (11). It is therefore possible to provide a liquid crystal display device including the signal distribution circuit (3) in which, even in a case where a leaking part (a defect part) is generated in any of the driving TFT elements (7), it does not take long to restore the leaking part, and productivity can be improved, the driving TFT elements (7) keeping respective channel widths identical to one another even after the leaking part is restored.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: May 13, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinya Tanaka, Tetsuo Kikuchi, Junya Shimada, Masahiro Yoshida, Isao Ogasawara, Satoshi Horiuchi
  • Patent number: 8659726
    Abstract: Transflective-type and reflection type liquid crystal display devices having a high image quality are provided with a good production efficiency. A liquid crystal display device according to the present invention is a liquid crystal display device which includes; a first substrate and a second substrate between which liquid crystal is interposed; a first electrode and a second electrode formed on the first substrate for applying a voltage for controlling an orientation of the liquid crystal; a transistor having an electrode which is electrically connected to the first electrode; a metal layer being formed on the first substrate and including a protrusion, a recess, or an aperture; and a reflective layer formed above the metal layer on the first substrate for reflecting incident light toward a display surface. The metal layer is made of a same material as that of a gate electrode of the transistor.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: February 25, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hajime Imai, Tetsuo Kikuchi, Hideki Kitagawa, Yoshihito Hara, Junya Shimada, Mitsunori Imade, Yoshiharu Kataoka
  • Patent number: 8654108
    Abstract: In a liquid crystal display device provided with a monolithic gate driver, a panel frame area is to be reduced as compared with a conventional configuration so that the device size can be reduced. In a region on an array substrate located outside of a display region, a third metal (503) is formed as a metal film in addition to a source metal (501) and a gate metal (502). The source metal (501) forms a wiring pattern that includes source electrodes of thin film transistors disposed in a pixel circuit and a gate driver, and the gate metal (502) forms a wiring pattern that includes gate electrodes of the thin film transistors. The third metal (503) is electrically connected to at least one of the source metal (501) and the gate metal (502) through a contact.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: February 18, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinya Tanaka, Tetsuo Kikuchi, Junya Shimada, Takuya Watanabe
  • Patent number: 8586987
    Abstract: A second stem wires (17c), formed by a reflective pixel electrode layer formed as a different layer from first stem wires (17a), is provided in such a way as to extend along a long side of its adjacent one of the first stem wires (17a). This makes it possible to achieve a TFT array substrate (1) on which a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) have been monolithically formed, wherein the width of a frame part in which the a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) are formed can be reduced.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: November 19, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Kikuchi, Shinya Tanaka, Junya Shimada, Chikao Yamasaki
  • Patent number: 8581257
    Abstract: The circuit board (1) of the present invention includes a plurality of transistor elements provided on a single insulating substrate (2) for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT (10) having a channel layer (11) formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT (20) having a channel layer (21) formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT (10) and the a-Si TFT (20) is a bottom-gate transistor.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: November 12, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsuhito Murai, Shinya Tanaka, Hideki Kitagawa, Hajime Imai, Mitsunori Imade, Tetsuo Kikuchi, Kazunori Morimoto, Junya Shimada, Jun Nishimura
  • Patent number: 8575620
    Abstract: The present invention provides a circuit board with a reduced circuit area, and a display device comprising the circuit board and a narrower picture frame. The circuit board of the present invention comprises: a bottom gate thin film transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and a top gate thin film transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor layer and the second semiconductor layer are formed from the same material, and the first drain electrode or the first source electrode and the second gate electrode are connected without interposing any other thin film transistor therebetween, and have the same electric potential.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Chikao Yamasaki, Shinya Tanaka, Tetsuo Kikuchi, Junya Shimada
  • Patent number: 8559588
    Abstract: Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.
    Type: Grant
    Filed: December 25, 2009
    Date of Patent: October 15, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Kikuchi, Shinya Tanaka, Chikao Yamasaki, Junya Shimada
  • Publication number: 20130214279
    Abstract: A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 22, 2013
    Inventors: Jun Nishimura, Hideki Kitagawa, Atsuhito Murai, Hajime Imai, Shinya Tanaka, Mitsunori Imade, Tetsuo Kikuchi, Junya Shimada, Kazunori Morimoto
  • Publication number: 20130201610
    Abstract: The present invention provides a circuit board with a reduced circuit area, and a display device comprising the circuit board and a narrower picture frame. The circuit board of the present invention comprises: a bottom gate thin film transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and a top gate thin film transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor layer and the second semiconductor layer are formed from the same material, and the first drain electrode or the first source electrode and the second gate electrode are connected without interposing any other thin film transistor therebetween, and have the same electric potential.
    Type: Application
    Filed: January 25, 2011
    Publication date: August 8, 2013
    Inventors: Chikao Yamasaki, Shinya Tanaka, Tetsuo Kikuchi, Junya Shimada
  • Publication number: 20130146866
    Abstract: A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.
    Type: Application
    Filed: March 2, 2011
    Publication date: June 13, 2013
    Inventors: Hideki Kitagawa, Shinya Tanaka, Hajime Imai, Atsuhito Murai, Mitsunori Imade, Tetsuo Kikuchi, Kazunori Morimoto, Junya Shimada, Jun Nishimura
  • Publication number: 20130092927
    Abstract: The circuit board (1) of the present invention includes a plurality of transistor elements provided on a single insulating substrate (2) for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT (10) having a channel layer (11) formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT (20) having a channel layer (21) formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT (10) and the a-Si TFT (20) is a bottom-gate transistor.
    Type: Application
    Filed: January 17, 2011
    Publication date: April 18, 2013
    Inventors: Atsuhito Murai, Shinya Tanaka, Hideki Kitagawa, Hajime Imai, Mitsunori Imade, Tetsuo Kikuchi, Kazunori Morimoto, Junya Shimada, Jun Nishimura