Patents by Inventor Junya Shirakura

Junya Shirakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8384619
    Abstract: When switching a motion blur pointer image to a normal pointer image, an intermediate pointer image is displayed between the motion blur pointer image and the normal pointer image. The intermediate pointer image is a rectangle, and coordinates of vertexes of the rectangle are composed of coordinates of vertexes of the motion blur pointer image and the next normal pointer image.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: February 26, 2013
    Assignee: Yazaki Corporation
    Inventors: Junya Shirakura, Kazuyoshi Ogasawara
  • Publication number: 20080018597
    Abstract: When switching a motion blur pointer image to a normal pointer image, an intermediate pointer image is displayed between the motion blur pointer image and the normal pointer image. The intermediate pointer image is a rectangle, and coordinates of vertexes of the rectangle are composed of coordinates of vertexes of the motion blur pointer image and the next normal pointer image.
    Type: Application
    Filed: April 11, 2007
    Publication date: January 24, 2008
    Applicant: YAZAKI CORPORATION
    Inventors: Junya Shirakura, Kazuyoshi Ogasawara
  • Patent number: 6396087
    Abstract: In a circuit in which logic cells are regularly arranged, to supply to a substrate substrate potentials different from a power supply voltage and ground voltage which are supplied to sources of transistors in the cell, substrate potential supplying cells are arranged in a region in which the logic cells are arranged. The substrate potential supplying cells are connected to the substrate potentials through an n-type substrate potential NSUB line and p-type substrate potential PSUB line. The substrate potentials are supplied to apply them to the substrate. If the substrate potential lines are arranged in the logic cell region, the element area is greatly reduced. However, using the substrate potential supplying cells VSC can improve area efficiency.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: May 28, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Kitabayashi, Tatsuya Higashi, Ryoko Usuba, Junya Shirakura